Unaligned Memory Access Behavior in ARM Cortex-M Processors

ARM Cortex-M Unaligned Memory Access and Address Truncation

The issue at hand revolves around the unexpected memory behavior observed when executing a sequence of ARM assembly instructions involving unaligned memory accesses. The code in question attempts to store 32-bit values at memory addresses incremented by 3 bytes, resulting in a memory layout that does not match the programmer’s expectations. Specifically, the memory contents after execution appear as follows:

0x40000000: 88 77 66 55 CC BB AA 99 11 FF EE DD

This behavior is not a bug but rather a consequence of how ARM Cortex-M processors handle unaligned memory accesses. Understanding this behavior requires a deep dive into the ARM architecture, particularly the handling of memory addresses and data alignment.

Memory Address Truncation Due to Unaligned Access

ARM Cortex-M processors, like many other RISC architectures, are designed to optimize performance and simplify hardware by enforcing certain alignment rules. When a program attempts to access memory at an unaligned address, the processor may truncate the address to the nearest aligned boundary. This truncation is a hardware-level behavior that ensures compatibility with the memory subsystem and avoids complex and costly unaligned access handling.

In the provided code, the addresses used for storing 32-bit values are incremented by 3 bytes, resulting in unaligned addresses:

LDR R1,=0X40000000
LDR R2,=0X11223344
STR R2,[R1]          // Store at 0x40000000 (aligned)
ADD R1,R1,#3
LDR R2,=0X55667788
STR R2,[R1]          // Store at 0x40000003 (unaligned)
ADD R1,R1,#3
LDR R2,=0X99AABBCC
STR R2,[R1]          // Store at 0x40000006 (unaligned)
ADD R1,R1,#3
LDR R2,=0XDDEEFF11
STR R2,[R1]          // Store at 0x40000009 (unaligned)

The ARM Cortex-M processor truncates these unaligned addresses to the nearest 4-byte boundary:

• 0x40000003 is truncated to 0x40000000
• 0x40000006 is truncated to 0x40000004
• 0x40000009 is truncated to 0x40000008

This truncation explains the observed memory layout. The 32-bit values are stored at the truncated addresses, overwriting portions of the previously stored data.

Resolving Unaligned Access Issues with Proper Alignment and Memory Barriers

To avoid unintended memory behavior due to unaligned accesses, developers must ensure that memory addresses are properly aligned for the data types being accessed. For 32-bit data, addresses should be aligned to 4-byte boundaries. Additionally, understanding and using memory barriers can help ensure that memory operations are performed in the intended order.

Ensuring Proper Alignment

The first step in resolving this issue is to modify the code to use aligned addresses. Instead of incrementing the address by 3 bytes, the address should be incremented by 4 bytes to maintain alignment:

LDR R1,=0X40000000
LDR R2,=0X11223344
STR R2,[R1]          // Store at 0x40000000 (aligned)
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0X55667788
STR R2,[R1]          // Store at 0x40000004 (aligned)
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0X99AABBCC
STR R2,[R1]          // Store at 0x40000008 (aligned)
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0XDDEEFF11
STR R2,[R1]          // Store at 0x4000000C (aligned)

With this modification, the memory layout will match the programmer’s expectations:

0x40000000: 44 33 22 11 88 77 66 55 CC BB AA 99 11 FF EE DD

Using Memory Barriers

In some cases, ensuring proper alignment may not be sufficient, especially when dealing with complex memory systems or multi-core processors. Memory barriers can be used to enforce the correct ordering of memory operations. ARM provides several memory barrier instructions, such as DMB (Data Memory Barrier), DSB (Data Synchronization Barrier), and ISB (Instruction Synchronization Barrier).

For example, if the code is part of a larger system where memory operations need to be synchronized, a DMB instruction can be inserted to ensure that all previous memory accesses are completed before proceeding:

LDR R1,=0X40000000
LDR R2,=0X11223344
STR R2,[R1]          // Store at 0x40000000 (aligned)
DMB                  // Data Memory Barrier
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0X55667788
STR R2,[R1]          // Store at 0x40000004 (aligned)
DMB                  // Data Memory Barrier
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0X99AABBCC
STR R2,[R1]          // Store at 0x40000008 (aligned)
DMB                  // Data Memory Barrier
ADD R1,R1,#4         // Increment by 4 bytes
LDR R2,=0XDDEEFF11
STR R2,[R1]          // Store at 0x4000000C (aligned)

Handling Unaligned Accesses Explicitly

In some scenarios, unaligned accesses may be unavoidable. In such cases, ARM processors provide mechanisms to handle unaligned accesses explicitly. For example, the LDREX and STREX instructions can be used to perform atomic read-modify-write operations, which can be useful when dealing with unaligned data.

Additionally, some ARM processors support hardware unaligned access handling, but this feature may come with a performance penalty. Developers should consult the processor’s reference manual to determine the best approach for their specific use case.

Summary of Key Points

• ARM Cortex-M processors truncate unaligned memory addresses to the nearest aligned boundary, leading to unexpected memory behavior.
• Proper alignment of memory addresses is essential to avoid unintended memory overwrites.
• Memory barriers can be used to enforce the correct ordering of memory operations in complex systems.
• Explicit handling of unaligned accesses may be necessary in certain scenarios, and developers should consult the processor’s reference manual for guidance.

By understanding and addressing these issues, developers can ensure that their ARM Cortex-M applications behave as intended and avoid subtle memory-related bugs.