UART DMA Configuration and FIFO Interaction in ARM-Based Microcontrollers

UART FIFO and DMA Mode Configuration in LPC17xx and Similar ARM Microcontrollers

The integration of UART (Universal Asynchronous Receiver/Transmitter) with DMA (Direct Memory Access) in ARM-based microcontrollers, such as the NXP LPC17xx series, is a powerful feature that can significantly enhance data transfer efficiency. However, the interaction between UART FIFOs (First-In-First-Out buffers) and DMA modes is often misunderstood, leading to configuration challenges. This post delves into the intricacies of UART FIFO and DMA mode configuration, focusing on the LPC17xx series but with principles applicable to other ARM-based microcontrollers.

UART FIFO Enable and DMA Mode Selection

The UART FIFO Control Register (FCR) in the LPC17xx series plays a pivotal role in enabling FIFOs and selecting DMA modes. The FCR register contains two critical bits: the FIFO Enable bit (bit 0) and the DMA Mode Select bit (bit 3). When the FIFO Enable bit is set to 1, both the UART RX and TX FIFOs are activated, and the DMA Mode Select bit becomes relevant. The DMA Mode Select bit determines whether the UART will generate DMA requests to service the FIFOs.

The relationship between the FIFO Enable bit and the DMA Mode Select bit is crucial. The DMA Mode Select bit only has an effect when the FIFOs are enabled. This means that DMA requests are generated based on the FIFO trigger levels or character timeout events. For instance, in DMA mode, the receiver DMA request is asserted when the receiver FIFO level equals or exceeds the trigger level, or when a character timeout occurs.

The specification suggests that enabling the FIFO also enables the DMA mode, but this is not entirely accurate. Enabling the FIFO merely allows the DMA mode to be selected. The DMA mode itself must be explicitly configured, and the DMA controller must be set up to handle the UART’s DMA requests. This distinction is critical for proper UART-DMA operation.

Misinterpretation of Automatic DMA Operation

A common misconception is that enabling the FIFO and DMA mode results in automatic DMA operation. This is not the case. While the FIFO and DMA mode enable the generation of DMA requests, the actual DMA transfers must be configured and managed by the software. The DMA controller must be programmed with the appropriate source and destination addresses, transfer size, and other parameters.

The UART’s DMA mode is designed to offload the CPU from handling individual byte transfers, but it does not eliminate the need for software configuration. The DMA controller must be initialized to respond to the UART’s DMA requests, and the UART must be configured to generate these requests based on FIFO levels or timeout events.

In summary, the UART’s DMA mode is not automatic; it requires explicit configuration of both the UART and the DMA controller. The FIFO enable bit and DMA mode select bit in the FCR register are the starting points, but additional setup is necessary to achieve seamless UART-DMA operation.

Troubleshooting UART-DMA Configuration Issues

When configuring UART with DMA, several issues can arise, often due to misunderstandings of the UART and DMA interaction. Below are some common problems and their solutions.

DMA Requests Not Generated

If DMA requests are not being generated, the first step is to verify that the FIFO Enable bit and DMA Mode Select bit in the UART FCR register are correctly set. The FIFO Enable bit must be set to 1 to enable the FIFOs, and the DMA Mode Select bit must be set to 1 to enable DMA mode. Additionally, ensure that the DMA controller is properly configured to handle the UART’s DMA requests.

Incorrect FIFO Trigger Levels

The UART’s FIFO trigger levels determine when DMA requests are generated. If the trigger levels are set too high or too low, DMA requests may not occur as expected. The trigger levels should be set based on the expected data rate and the desired latency. For example, if the UART is receiving data at a high rate, a lower trigger level may be appropriate to ensure timely DMA transfers.

DMA Transfer Stalls

DMA transfer stalls can occur if the DMA controller is not configured to handle the UART’s DMA requests efficiently. Ensure that the DMA controller is set up with the correct source and destination addresses, transfer size, and priority. Additionally, check that the DMA controller is not being starved of bus access by other bus masters.

UART FIFO Overflow or Underflow

UART FIFO overflow or underflow can occur if the DMA transfers are not keeping up with the data rate. This can be caused by incorrect DMA configuration, insufficient DMA bandwidth, or high system load. To mitigate this, ensure that the DMA controller is configured with sufficient bandwidth and priority. Additionally, consider using larger FIFOs or adjusting the UART baud rate to better match the data rate.

Character Timeout Issues

Character timeout events can trigger DMA requests if the UART does not receive a complete character within a specified time. If character timeouts are causing unexpected DMA requests, adjust the timeout value or disable the character timeout feature if it is not needed.

Detailed Configuration Steps for UART-DMA Operation

To achieve reliable UART-DMA operation, follow these detailed configuration steps:

1. Enable UART FIFOs: Set the FIFO Enable bit (bit 0) in the UART FCR register to 1. This enables both the RX and TX FIFOs.

2. Select DMA Mode: Set the DMA Mode Select bit (bit 3) in the UART FCR register to 1. This enables DMA mode for the UART.

3. Configure DMA Controller: Program the DMA controller with the appropriate source and destination addresses, transfer size, and other parameters. Ensure that the DMA controller is set up to handle the UART’s DMA requests.

4. Set FIFO Trigger Levels: Configure the UART FIFO trigger levels based on the expected data rate and desired latency. The trigger levels determine when DMA requests are generated.

5. Enable DMA Requests: Ensure that the UART is configured to generate DMA requests based on FIFO levels or character timeout events.

6. Initialize UART and DMA: Initialize the UART and DMA controller with the configured settings. Verify that the DMA controller is ready to handle the UART’s DMA requests.

7. Start UART Operation: Start UART operation and monitor the DMA transfers. Ensure that the DMA controller is handling the UART’s DMA requests efficiently and that there are no FIFO overflow or underflow issues.

8. Adjust Configuration as Needed: Based on the observed performance, adjust the FIFO trigger levels, DMA configuration, or UART baud rate as needed to optimize UART-DMA operation.

Conclusion

Configuring UART with DMA in ARM-based microcontrollers requires a thorough understanding of the UART FIFO and DMA mode interaction. The FIFO Enable bit and DMA Mode Select bit in the UART FCR register are critical for enabling DMA operation, but additional configuration of the DMA controller is necessary to achieve reliable data transfers. By following the detailed configuration steps and troubleshooting common issues, developers can achieve efficient UART-DMA operation in their embedded systems.