Understanding PMU Event Counters on ARM Cortex-A72 and Cortex-R5F
The Performance Monitoring Unit (PMU) in ARM Cortex-A72 and Cortex-R5F processors is a critical component for profiling and optimizing system performance. The PMU provides a set of counters that can be programmed to track specific architectural and microarchitectural events. Architectural events are those defined by the ARM architecture, such as instruction retirements or cache misses, while microarchitectural events are implementation-specific, such as pipeline stalls or branch mispredictions. These events are essential for understanding the behavior of the system, identifying bottlenecks, and optimizing both software and hardware configurations.
The ARM Cortex-A72, a high-performance processor core designed for mobile and enterprise applications, and the Cortex-R5F, a real-time processor core optimized for safety-critical applications, both feature PMUs with varying capabilities. The Cortex-A72 PMU supports a wide range of events due to its complex out-of-order execution pipeline, while the Cortex-R5F PMU is more limited but still provides valuable insights into real-time system performance.
To retrieve the number of PMU events, developers must understand the specific PMU registers and their configurations. The PMU in both Cortex-A72 and Cortex-R5F processors is accessed through a set of Performance Monitor Control Registers (PMCRs) and Event Counter Registers (PMEVCNTRs). These registers allow developers to enable, configure, and read event counters. Additionally, the PMU Event Selection Registers (PMSELRs) are used to select which event is being monitored by a specific counter.
Challenges in Accessing PMU Event Counts and Common Pitfalls
One of the primary challenges in accessing PMU event counts is the complexity of the PMU register interface and the need for precise configuration. The PMU registers are memory-mapped and require specific sequences of writes and reads to ensure accurate event counting. Misconfigurations can lead to incorrect event counts or even system instability. For example, failing to enable the PMU before configuring event counters will result in no events being counted. Similarly, not clearing counters before starting a new measurement can lead to skewed results.
Another common pitfall is the misinterpretation of event codes. Each PMU event is identified by a unique event code, which must be correctly programmed into the PMEVTYPER (Event Type) registers. The event codes for architectural events are standardized across ARM processors, but microarchitectural event codes are implementation-specific and must be carefully referenced from the Technical Reference Manual (TRM) for the specific processor. Using incorrect event codes will result in monitoring the wrong events or no events at all.
The Cortex-A72 and Cortex-R5F PMUs also have limitations on the number of simultaneous events that can be monitored. The Cortex-A72 typically supports up to six configurable counters, while the Cortex-R5F supports fewer. This limitation requires developers to prioritize which events are most critical for their analysis. Additionally, some events may require specific hardware configurations or privileges, such as enabling certain performance monitoring features in the system control registers.
Another challenge is the handling of counter overflows. PMU counters are typically 32-bit or 64-bit registers, and they can overflow if the event count exceeds the maximum value. Developers must implement mechanisms to handle overflows, such as periodic sampling or using overflow interrupts. Failure to handle overflows can result in lost data and inaccurate performance measurements.
Configuring and Reading PMU Event Counters on Cortex-A72 and Cortex-R5F
To configure and read PMU event counters on the ARM Cortex-A72 and Cortex-R5F, developers must follow a systematic approach. The first step is to enable the PMU by setting the appropriate bits in the PMCR (Performance Monitor Control Register). This register controls the global enable/disable state of the PMU and resets the counters. The PMCR also allows developers to specify the number of counters available and whether cycle counting is enabled.
Once the PMU is enabled, the next step is to configure the event counters. This involves selecting the event to be monitored by writing the appropriate event code to the PMEVTYPER register. For example, to monitor the number of L1 data cache misses on the Cortex-A72, the event code 0x04 must be written to the PMEVTYPER register. The Cortex-R5F may use a different event code for the same event, so it is crucial to consult the TRM for the correct codes.
After configuring the event counters, developers must clear the counters to ensure they start from zero. This is done by writing to the PMEVCNTR registers. Once the counters are cleared, the PMU can be started by setting the appropriate bits in the PMCR. The system will then begin counting the specified events.
To read the event counts, developers can directly read the PMEVCNTR registers. However, it is important to consider the timing of the reads to avoid race conditions or counter overflows. For long-running measurements, developers may need to implement periodic sampling or use overflow interrupts to ensure accurate counts. The PMOVSSET (Overflow Flag Status) register can be used to detect counter overflows and trigger appropriate handling routines.
For developers working in a Linux environment, the perf framework provides a higher-level interface for accessing PMU events. The perf tool allows developers to specify events using symbolic names and handles many of the low-level details of PMU configuration. For example, the command perf stat -e L1-dcache-load-misses ./program will run the specified program and report the number of L1 data cache load misses. The perf framework is particularly useful for quick profiling and does not require detailed knowledge of the PMU registers.
For bare-metal systems, ARM Development Studio provides a comprehensive environment for PMU configuration and event monitoring. The Development Studio includes example code and tools for setting up the PMU and reading event counts. This is particularly useful for developers working on custom firmware or real-time systems where direct access to the PMU registers is required.
In conclusion, retrieving PMU architectural and microarchitectural event counts on ARM Cortex-A72 and Cortex-R5F processors requires a deep understanding of the PMU register interface and careful configuration. Developers must be aware of the challenges and pitfalls associated with PMU event counting and follow a systematic approach to ensure accurate and reliable measurements. Whether using low-level register access or higher-level tools like perf or ARM Development Studio, the PMU provides invaluable insights into system performance and is a critical tool for optimization and debugging.
