Preventing Non-Secure Malicious Access in ARM Cortex-M TrustZone Systems

ARM Cortex-M TrustZone Memory Access Vulnerabilities

In ARM Cortex-M systems utilizing TrustZone technology, one of the most critical security challenges is ensuring that Non-Secure (NS) code cannot maliciously access Secure (S) memory regions. This issue arises due to the dual mapping of memory regions in both Secure and Non-Secure address spaces, which can lead to unintended access to sensitive data or code. The problem is exacerbated when the system is not properly configured to enforce strict boundaries between Secure and Non-Secure memory regions.

The ARM Cortex-M architecture, particularly in Armv8-M, introduces features like the Implementation Defined Attribution Unit (IDAU), Security Attribution Unit (SAU), and Memory Protection Unit (MPU) to manage memory security attributes. However, these features must be correctly configured and complemented by system-level security controllers to prevent unauthorized access. Misconfigurations or oversights in these settings can lead to scenarios where Non-Secure code can access Secure memory, potentially compromising the entire system’s security.

The core of the issue lies in the memory mapping and the security attributes assigned to different memory regions. For instance, if a physical RAM location is mapped to both Secure and Non-Secure address spaces without proper isolation, a Non-Secure access to the Non-Secure address could inadvertently access Secure data. This is particularly problematic in systems where Secure and Non-Secure regions are not strictly segregated, leading to potential security breaches.

Memory Mapping Duplication and Security Attribute Misconfiguration

The primary cause of Non-Secure malicious access in ARM Cortex-M TrustZone systems is the duplication of memory mappings in both Secure and Non-Secure address spaces without proper isolation. This duplication can occur when the system designer configures the IDAU and SAU to allow overlapping memory regions in both Secure and Non-Secure worlds. The IDAU and SAU are responsible for defining the security attributes of memory regions, but they do not inherently prevent duplication unless explicitly configured to do so.

Another significant cause is the misconfiguration or underutilization of the Memory Protection Unit (MPU). While the MPU is a powerful tool for enforcing memory access permissions, it does not define the security attributes of memory regions. Instead, it relies on the security attributes defined by the IDAU and SAU. If the MPU is not properly configured to enforce strict access controls based on these attributes, it can fail to prevent Non-Secure code from accessing Secure memory.

Additionally, the absence or improper implementation of a system security controller can lead to vulnerabilities. The system security controller acts as a gatekeeper, ensuring that each memory address is only accessible in either the Secure or Non-Secure region at any given time. Without this controller, the system may allow simultaneous access to the same physical memory location from both Secure and Non-Secure regions, leading to potential security breaches.

Implementing System Security Controllers and Proper Memory Isolation

To address the issue of Non-Secure malicious access in ARM Cortex-M TrustZone systems, it is essential to implement a robust system security controller and ensure proper memory isolation. The system security controller should act as a gate component, filtering all memory transactions to ensure that each physical memory location is only accessible in either the Secure or Non-Secure region at any given time. This controller should be accessible only by Secure transactions and should hold all the register fields necessary to modify the configurable aspects of system security, such as the boundary between Secure and Non-Secure memory in RAM.

The first step in implementing this solution is to configure the IDAU and SAU to define the security attributes of the memory map correctly. The IDAU and SAU should be set up to ensure that there is no duplication of memory mappings in both Secure and Non-Secure regions. This can be achieved by carefully defining the memory regions in the IDAU and SAU configuration registers, ensuring that each physical memory location is assigned a unique security attribute.

Next, the MPU should be configured to enforce strict access controls based on the security attributes defined by the IDAU and SAU. The MPU should be programmed to prevent Non-Secure access to Secure memory regions and to enforce the appropriate access permissions for each memory region. This includes setting up the MPU regions to cover all memory areas and configuring the access permissions to match the security attributes defined by the IDAU and SAU.

Finally, the system security controller should be implemented to act as a gatekeeper, ensuring that all memory transactions are properly filtered and that each memory address is only accessible in either the Secure or Non-Secure region. The system security controller should be designed to handle all memory transactions, including those from peripherals, and should be capable of dynamically modifying the security attributes of memory regions as needed.

In addition to these steps, it is also important to implement proper debugging and monitoring mechanisms to detect and respond to any potential security breaches. This includes setting up secure debug channels, implementing secure boot processes, and using hardware-based security features like TrustZone to protect sensitive data and code.

By following these steps and ensuring proper configuration of the IDAU, SAU, MPU, and system security controller, it is possible to prevent Non-Secure malicious access in ARM Cortex-M TrustZone systems and ensure the security and integrity of the system.

Detailed Configuration Steps for IDAU, SAU, and MPU

To provide a more detailed guide, let’s break down the configuration steps for the IDAU, SAU, and MPU:

1. IDAU Configuration:

   • Define the memory regions in the IDAU configuration registers.
   • Assign unique security attributes to each memory region.
   • Ensure that there is no overlap between Secure and Non-Secure memory regions.

2. SAU Configuration:

   • Configure the SAU to define the security attributes of the memory map.
   • Set up the SAU regions to cover all memory areas.
   • Ensure that the SAU regions do not overlap with each other.

3. MPU Configuration:

   • Program the MPU to enforce strict access controls based on the security attributes defined by the IDAU and SAU.
   • Set up the MPU regions to cover all memory areas.
   • Configure the access permissions for each MPU region to match the security attributes defined by the IDAU and SAU.

4. System Security Controller Implementation:

   • Design the system security controller to act as a gatekeeper for all memory transactions.
   • Ensure that the system security controller is accessible only by Secure transactions.
   • Implement register fields in the system security controller to modify the configurable aspects of system security, such as the boundary between Secure and Non-Secure memory in RAM.

5. Debugging and Monitoring:

   • Set up secure debug channels to detect and respond to potential security breaches.
   • Implement secure boot processes to ensure the integrity of the system at startup.
   • Use hardware-based security features like TrustZone to protect sensitive data and code.

By following these detailed configuration steps, you can ensure that your ARM Cortex-M TrustZone system is properly secured against Non-Secure malicious access and that the integrity of your system is maintained.

Example Configuration Table

Below is an example table illustrating the configuration of IDAU, SAU, and MPU for a typical ARM Cortex-M TrustZone system:

Memory Region	Start Address	End Address	Security Attribute	MPU Access Permissions
Secure RAM	0x02000000	0x0200FFFF	Secure	Read/Write (Secure Only)
Non-Secure RAM	0x01000000	0x0100FFFF	Non-Secure	Read/Write (Non-Secure Only)
Secure Flash	0x08000000	0x0801FFFF	Secure	Read/Execute (Secure Only)
Non-Secure Flash	0x00000000	0x0001FFFF	Non-Secure	Read/Execute (Non-Secure Only)

This table provides a clear overview of how memory regions should be configured in the IDAU, SAU, and MPU to ensure proper isolation and security in an ARM Cortex-M TrustZone system.

Conclusion

Preventing Non-Secure malicious access in ARM Cortex-M TrustZone systems requires a comprehensive approach that includes proper configuration of the IDAU, SAU, and MPU, as well as the implementation of a robust system security controller. By following the detailed steps outlined in this guide, you can ensure that your system is properly secured against potential security breaches and that the integrity of your system is maintained. Additionally, implementing proper debugging and monitoring mechanisms will help detect and respond to any potential security threats, further enhancing the security of your system.