NIC400 AXI4 Bridge Configuration and Outstanding Transaction Limitation
The NIC400 interconnect is a highly configurable and scalable interconnect IP from ARM, designed to support AMBA AXI, AHB, and APB protocols. It is widely used in ARM-based SoC designs to manage communication between multiple masters and slaves. One of the key features of the NIC400 is its ability to control the number of outstanding transactions, which is critical for managing system performance, ensuring data coherency, and meeting specific design requirements.
In this scenario, the goal is to configure the NIC400 AXI4 bridge such that the master interface is limited to only one outstanding transaction at a time, regardless of whether it is a read or write transaction. This requirement is often imposed to simplify system design, reduce complexity in arbitration, or meet specific latency and bandwidth constraints. However, the initial configuration, which involved setting the total issuing limit to 1 and the read and write issuing limits to 1, did not achieve the desired behavior. This suggests a misunderstanding of how the NIC400 handles outstanding transactions and how its configuration parameters interact.
Misconfiguration of NIC400 Transaction Issuing Limits
The NIC400 provides several configuration parameters to control the number of outstanding transactions, including the total number of outstanding transactions, the number of outstanding read transactions, and the number of outstanding write transactions. These parameters are typically set in the NIC400 configuration registers and are enforced by the interconnect logic.
The primary issue in this case stems from the incorrect assumption that setting the total issuing limit to 1 and the read and write issuing limits to 1 would inherently prevent simultaneous read and write transactions. However, the NIC400 treats read and write transactions independently, meaning that the read and write issuing limits are enforced separately. As a result, even if the total issuing limit is set to 1, the NIC400 may still allow one read and one write transaction to be outstanding simultaneously, provided that the read and write issuing limits are both set to 1.
This behavior is consistent with the AMBA AXI protocol, which allows separate channels for read and write transactions. The AXI protocol defines independent channels for address, data, and response phases, enabling concurrent read and write operations. The NIC400, being AXI-compliant, adheres to this protocol and does not inherently restrict the combination of read and write transactions unless explicitly configured to do so.
Additionally, the NIC400’s arbitration logic may prioritize certain transactions based on their type, source, or destination, further complicating the enforcement of a strict one-transaction-at-a-time policy. For example, if a read transaction is already outstanding, a write transaction may still be initiated if the write issuing limit has not been reached, even if the total issuing limit is set to 1.
Correct Configuration and Verification of NIC400 Transaction Limits
To achieve the desired behavior of limiting the master interface to only one outstanding transaction at a time, regardless of whether it is a read or write transaction, the NIC400 configuration must be adjusted to enforce a combined limit on read and write transactions. This can be accomplished by setting the total issuing limit to 1 and ensuring that the read and write issuing limits are also set to 1. However, additional measures may be required to prevent the NIC400 from allowing simultaneous read and write transactions.
One approach is to implement a custom arbitration scheme that enforces a strict one-transaction-at-a-time policy. This can be done by modifying the NIC400 configuration to prioritize one type of transaction (e.g., read) over the other (e.g., write) and ensuring that the arbitration logic does not allow overlapping transactions. For example, the NIC400 can be configured to prioritize read transactions and block write transactions until the read transaction is completed, or vice versa.
Another approach is to use the NIC400’s transaction ID management features to track and limit outstanding transactions. The NIC400 supports transaction IDs, which can be used to uniquely identify and manage transactions. By configuring the NIC400 to use a single transaction ID for all transactions, the interconnect can be forced to process one transaction at a time. This approach requires careful management of transaction IDs and may involve additional logic to ensure that the NIC400 does not issue new transactions until the current transaction is completed.
To verify that the NIC400 is correctly configured to limit outstanding transactions, a comprehensive verification strategy must be employed. This strategy should include both simulation and formal verification techniques to ensure that the NIC400 adheres to the desired transaction limits under all possible conditions.
Simulation-based verification should involve creating a testbench that exercises the NIC400 under various scenarios, including back-to-back read and write transactions, simultaneous read and write transactions, and transactions with different burst lengths and sizes. The testbench should monitor the NIC400’s behavior and check that the number of outstanding transactions does not exceed the configured limits. This can be done by tracking the AXI signals (e.g., ARVALID, AWVALID, RVALID, WVALID) and ensuring that only one transaction is active at any given time.
Formal verification can be used to mathematically prove that the NIC400’s configuration enforces the desired transaction limits. This involves creating formal properties that specify the expected behavior of the NIC400 and using a formal verification tool to check that these properties hold under all possible input conditions. For example, a formal property can be defined to assert that the NIC400 does not issue a new transaction until the current transaction is completed.
In addition to simulation and formal verification, it is important to review the NIC400’s configuration registers and ensure that they are correctly set to enforce the desired transaction limits. This includes checking the values of the total issuing limit, read issuing limit, and write issuing limit, as well as any other relevant configuration parameters. The ARM Technical Reference Manual (TRM) for the NIC400 should be consulted to ensure that the configuration is consistent with the intended behavior.
Finally, it is recommended to perform a thorough review of the NIC400’s arbitration logic and transaction ID management to ensure that they are correctly implemented and do not introduce any unintended behavior. This may involve analyzing the RTL code, reviewing synthesis reports, and performing timing analysis to ensure that the NIC400 meets the design requirements.
By following these steps, the NIC400 can be correctly configured and verified to limit the number of outstanding transactions to one, ensuring that the master interface adheres to the desired one-transaction-at-a-time policy. This approach not only addresses the immediate issue but also provides a robust framework for managing transaction limits in future designs.
