ARM Cortex-A7 Secure World Interrupt Handling in Trusty
When working with the ARM Cortex-A7 processor in a secure world environment such as Trusty, one of the critical challenges is ensuring that interrupts are correctly configured and received. The Cortex-A7, being part of the ARMv7-A architecture, supports both secure and non-secure states, and the handling of interrupts in these states requires careful configuration of the Generic Interrupt Controller (GIC) and the processor’s CPSR (Current Program Status Register). The issue at hand involves interrupts not being received in the secure world, despite the necessary configurations being seemingly in place. This problem can stem from a variety of causes, ranging from incorrect GIC configurations to improper handling of the FIQ (Fast Interrupt Request) bit in the CPSR.
The Cortex-A7’s GIC is responsible for managing interrupts, and it must be configured to route interrupts to the correct security state. In the secure world, interrupts are typically handled as FIQs, which are distinct from IRQs (Interrupt Requests) used in the non-secure world. The GIC must be programmed to ensure that interrupts are routed as FIQs to the secure world, and the processor must be configured to accept these FIQs. Additionally, the Trusty OS must be set up to handle these FIQs correctly. The failure to receive interrupts in the secure world suggests that one or more of these configurations may be incorrect or incomplete.
GIC Configuration and FIQ Bit Handling
The first step in diagnosing the issue is to examine the configuration of the GIC. The GIC is divided into several key registers, including the GICD_ITARGETSR (Interrupt Processor Targets Registers) and the GICD_ISENABLER (Interrupt Set Enable Registers). The GICD_ITARGETSR register is used to specify which CPU interfaces should receive a particular interrupt, while the GICD_ISENABLER register is used to enable specific interrupts. In the context of the secure world, it is essential to ensure that the GICD_ITARGETSR register is configured to route interrupts to the secure world, and that the GICD_ISENABLER register is set to enable the relevant interrupts.
Another critical aspect of GIC configuration is the handling of interrupt priorities. The GICD_IPRIORITYR (Interrupt Priority Registers) must be configured to assign appropriate priorities to the interrupts. In the secure world, interrupts with higher priority are more likely to be handled as FIQs. Therefore, it is important to ensure that the interrupts intended for the secure world are assigned higher priorities than those intended for the non-secure world.
In addition to GIC configuration, the handling of the FIQ bit in the CPSR is crucial. The CPSR contains a bit that determines whether FIQs are enabled or disabled. If this bit is not cleared, the processor will not accept FIQs, and interrupts will not be received in the secure world. The FIQ bit must be cleared to enable FIQs, and this is typically done during the initialization of the secure world environment. Failure to clear the FIQ bit is a common cause of interrupts not being received in the secure world.
Implementing Correct GIC and CPSR Configurations
To resolve the issue of interrupts not being received in the secure world, a systematic approach to configuring the GIC and CPSR is required. The first step is to verify that the GICD_ITARGETSR register is correctly configured to route interrupts to the secure world. This involves setting the appropriate bits in the GICD_ITARGETSR register to specify that the secure world should receive the interrupts. It is also important to ensure that the GICD_ISENABLER register is set to enable the relevant interrupts.
Next, the GICD_IPRIORITYR register must be configured to assign appropriate priorities to the interrupts. Interrupts intended for the secure world should be assigned higher priorities than those intended for the non-secure world. This ensures that the secure world interrupts are handled as FIQs, while the non-secure world interrupts are handled as IRQs.
Once the GIC is correctly configured, the next step is to ensure that the FIQ bit in the CPSR is cleared. This can be done by writing to the CPSR during the initialization of the secure world environment. The following code snippet demonstrates how to clear the FIQ bit in the CPSR:
MRS r0, CPSR ; Load the CPSR into register r0
BIC r0, r0, #0x40 ; Clear the FIQ bit (bit 6)
MSR CPSR_c, r0 ; Write the modified CPSR back
After clearing the FIQ bit, the processor will be able to accept FIQs, and interrupts should be received in the secure world. It is also important to ensure that the Trusty OS is correctly set up to handle these FIQs. This involves implementing the appropriate interrupt handler routines in the secure world and ensuring that they are correctly registered with the GIC.
In addition to the above steps, it is important to verify that the interrupt sources themselves are correctly configured. This includes ensuring that the SPI (Serial Peripheral Interface) and GPIO (General Purpose Input/Output) drivers are correctly initialized and that they are generating the expected interrupts. It may be necessary to debug the drivers to ensure that they are functioning correctly and that they are generating interrupts as expected.
Finally, it is important to consider the overall system configuration and ensure that there are no conflicts or misconfigurations that could be preventing interrupts from being received in the secure world. This includes checking the system memory map, ensuring that the secure and non-secure worlds are correctly partitioned, and verifying that there are no issues with the system clock or power management that could be affecting interrupt handling.
In conclusion, the issue of interrupts not being received in the secure world on the Cortex-A7 with Trusty can be resolved by carefully configuring the GIC and CPSR, ensuring that the FIQ bit is cleared, and verifying that the interrupt sources and system configuration are correct. By following the steps outlined above, it should be possible to diagnose and resolve the issue, allowing interrupts to be correctly received and handled in the secure world.
