ARM Cortex-A72 L2 Cache Miss Monitoring Challenges
The ARM Cortex-A72 processor is a high-performance CPU core designed for a wide range of applications, from mobile devices to embedded systems. One of the critical aspects of optimizing performance on the Cortex-A72 is understanding and monitoring cache behavior, particularly L2 cache misses. The L2 cache serves as an intermediary between the faster L1 cache and the slower main memory, and its efficiency directly impacts overall system performance. However, identifying and measuring L2 cache misses can be challenging due to the complexity of the Performance Monitoring Unit (PMU) events and their interpretation.
The Cortex-A72 Technical Reference Manual (TRM) lists several PMU events related to L2 cache activity, including L2D_CACHE_REFILL, L2D_CACHE_REFILL_LD, L2D_CACHE_REFILL_ST, and L2D_CACHE_INVAL. These events provide insights into cache refills and invalidations, but their exact meanings and how they relate to cache misses are not immediately obvious. This ambiguity can lead to confusion when attempting to measure the impact of L2 cache size on performance, such as comparing a 0.5MB L2 cache to a 1.0MB L2 cache.
To accurately monitor L2 cache misses, it is essential to understand the specific PMU events and their implications. This involves not only selecting the correct events but also interpreting the data they provide in the context of the system’s overall behavior. The goal is to identify the events that directly correlate with cache misses and use them to measure the performance impact of different cache sizes.
PMU Event Definitions and Their Relationship to L2 Cache Misses
The Cortex-A72 PMU provides a set of events that can be used to monitor various aspects of cache behavior. Among these, the events related to L2 cache refills and invalidations are particularly relevant for identifying cache misses. The key events to consider are L2D_CACHE_REFILL, L2D_CACHE_REFILL_LD, L2D_CACHE_REFILL_ST, and L2D_CACHE_INVAL.
The L2D_CACHE_REFILL event counts the number of times a cache line is refilled in the L2 cache. This refill can occur due to various reasons, such as a cache miss or the eviction of a cache line to make room for new data. The L2D_CACHE_REFILL_LD and L2D_CACHE_REFILL_ST events are more specific, counting refills that occur due to load and store operations, respectively. These events provide a more granular view of cache behavior, allowing for a detailed analysis of how different types of memory accesses impact cache performance.
The L2D_CACHE_INVAL event, on the other hand, counts the number of times a cache line is invalidated. Invalidation can occur for several reasons, such as when a cache line is evicted or when it is explicitly invalidated by software. While this event does not directly measure cache misses, it can provide valuable context for understanding cache behavior, particularly in systems where cache invalidation is frequent.
To accurately measure L2 cache misses, it is necessary to focus on the refill events, as these directly indicate when data was not found in the L2 cache and had to be fetched from main memory. The sum of the L2D_CACHE_REFILL_LD and L2D_CACHE_REFILL_ST events provides a comprehensive count of cache misses due to both load and store operations. This combined metric can be used to assess the overall impact of L2 cache size on performance, as it reflects the total number of times the cache failed to satisfy memory requests.
Implementing L2 Cache Miss Monitoring with Linux Perf
To monitor L2 cache misses on the Cortex-A72 using Linux perf, it is necessary to configure the PMU to count the relevant events and then use the perf tool to collect and analyze the data. The first step is to identify the event codes for the L2D_CACHE_REFILL_LD and L2D_CACHE_REFILL_ST events, which can be found in the Cortex-A72 TRM. These event codes are then passed to the perf tool to start counting.
Once the events are configured, the perf tool can be used to run a workload and collect data on cache refills. The collected data can then be analyzed to determine the number of L2 cache misses and their impact on performance. This analysis can be performed using various perf subcommands, such as perf stat, which provides a summary of event counts, or perf record and perf report, which allow for more detailed analysis of event timing and distribution.
In addition to monitoring cache refills, it is also useful to monitor other related events, such as L2D_CACHE_INVAL, to gain a more complete understanding of cache behavior. This can help identify patterns of cache invalidation that may be contributing to cache misses and provide insights into potential optimizations.
When comparing the performance of systems with different L2 cache sizes, it is important to ensure that the workloads being tested are representative of the actual use case. This includes considering factors such as the size and access patterns of the data being processed, as well as the impact of other system components, such as the memory controller and interconnect. By carefully controlling these variables and accurately measuring cache misses, it is possible to make meaningful comparisons between different cache configurations and identify the optimal setup for a given application.
In conclusion, monitoring L2 cache misses on the ARM Cortex-A72 requires a thorough understanding of the PMU events related to cache refills and invalidations. By focusing on the L2D_CACHE_REFILL_LD and L2D_CACHE_REFILL_ST events and using the Linux perf tool to collect and analyze data, it is possible to accurately measure cache misses and assess their impact on performance. This information can then be used to optimize cache configuration and improve overall system performance.
