Hybrid Prototyping for ARM SoC Design: Combining C/C++, SystemC, and RTL Simulation

ARM SoC Simulation Challenges with Mixed Abstraction Levels

The design and verification of ARM-based System-on-Chip (SoC) architectures often require simulation environments that can handle multiple abstraction levels. Traditional simulation methods, such as Fast Models, rely on virtual models written in high-level languages like C/C++ or SystemC. While these models are efficient for early-stage development and software validation, they lack the accuracy needed for RTL-level verification. Conversely, RTL simulations provide cycle-accurate results but are computationally expensive and slow, especially for large-scale SoCs. This creates a significant gap in the verification process, where designers need both the speed of high-level models and the accuracy of RTL simulations.

The challenge intensifies when integrating third-party IP blocks, custom RTL modules, and software stacks. For instance, an ARM Cortex-A series processor might be modeled in C++ for software development, while a custom accelerator or memory controller is implemented in RTL. Bridging these abstraction levels is critical to ensure functional correctness, performance validation, and system-level debugging. Without a hybrid approach, designers face inefficiencies in simulation speed, accuracy, and debugging capabilities, leading to prolonged development cycles and potential integration issues.

Limitations of Pure High-Level and RTL-Only Simulation Approaches

The limitations of pure high-level simulation approaches, such as ARM Fast Models, stem from their inability to capture low-level timing and hardware-specific behaviors. These models abstract away many details of the hardware, making them unsuitable for verifying cycle-accurate interactions between components. For example, a DMA controller modeled in C++ might not accurately reflect the timing of bus transactions on an AXI interconnect, leading to mismatches between simulation and actual hardware behavior.

On the other hand, RTL-only simulations, while accurate, are prohibitively slow for large-scale SoCs. Simulating an entire ARM-based SoC with multiple cores, peripherals, and interconnects at the RTL level can take hours or even days to complete a single test case. This makes it impractical for exhaustive verification, especially when validating complex use cases such as cache coherency, power management, or multi-core synchronization.

The absence of a hybrid simulation environment exacerbates these challenges. Designers are forced to choose between speed and accuracy, often leading to incomplete verification coverage. For instance, a software team might develop and test drivers using a high-level model, only to discover timing-related bugs during RTL simulation or, worse, during silicon bring-up. This disconnect between abstraction levels highlights the need for a hybrid prototyping solution that seamlessly integrates high-level models with RTL simulations.

Hybrid Prototyping Solutions for ARM SoC Design and Verification

Hybrid prototyping addresses the limitations of pure high-level and RTL-only simulations by combining the speed of high-level models with the accuracy of RTL simulations. This approach enables designers to simulate parts of the SoC at different abstraction levels, depending on the verification requirements. For example, the ARM Cortex processor and memory subsystem can be modeled in C++ or SystemC for fast simulation, while custom accelerators or peripherals are simulated at the RTL level for cycle-accurate validation.

Key Components of Hybrid Prototyping

1. High-Level Models: These models, typically written in C/C++ or SystemC, provide fast simulation speeds and are ideal for software development, early-stage validation, and system-level performance analysis. ARM Fast Models are a prime example, offering functional accuracy for ARM processors and peripherals.

2. RTL Simulations: RTL simulations provide cycle-accurate representations of hardware components, ensuring precise timing and functional correctness. These are essential for verifying low-level interactions, such as bus transactions, clock domain crossings, and power management sequences.

3. Transactors and Bridges: Transactors act as intermediaries between high-level models and RTL simulations, translating transactions between different abstraction levels. For example, a transactor can convert a high-level memory access request from a SystemC model into a detailed AXI bus transaction for RTL simulation.

4. Co-Simulation Environments: These environments integrate high-level models and RTL simulations into a unified framework, enabling seamless interaction between components at different abstraction levels. Tools like Cadence Palladium, Synopsys HAPS, and Mentor Veloce support hybrid prototyping by providing co-simulation capabilities.

Benefits of Hybrid Prototyping

1. Improved Simulation Speed: By simulating only the critical components at the RTL level and using high-level models for the rest of the system, hybrid prototyping significantly reduces simulation time. This allows designers to run more test cases and achieve higher verification coverage.

2. Enhanced Debugging Capabilities: Hybrid prototyping provides visibility into both high-level and low-level interactions, making it easier to identify and debug issues. For example, a designer can trace a software-driven memory access from the high-level model through the transactor and into the RTL simulation, pinpointing the exact source of a timing violation.

3. Early Software Development: High-level models enable software teams to develop and test drivers, firmware, and operating systems long before the RTL design is complete. This reduces time-to-market and ensures that software and hardware are co-verified early in the design cycle.

4. Scalability: Hybrid prototyping scales effectively for large-scale SoCs, allowing designers to simulate complex systems with multiple processors, interconnects, and peripherals. This is particularly important for ARM-based SoCs, which often include dozens of IP blocks and custom modules.

Implementation Considerations

1. Model Accuracy: High-level models must accurately represent the behavior of the corresponding hardware components, especially for critical functions like interrupt handling, cache coherency, and power management. Inaccuracies in the models can lead to mismatches between simulation and hardware behavior.

2. Transactor Design: Transactors must be carefully designed to ensure correct translation between abstraction levels. For example, a transactor converting AXI transactions must handle all AXI signals, including address, data, control, and response, while maintaining proper timing relationships.

3. Synchronization: Synchronizing high-level models and RTL simulations is critical to avoid race conditions and timing mismatches. This requires precise control over simulation clocks and event scheduling.

4. Tool Integration: Hybrid prototyping relies on the integration of multiple tools, including high-level simulators, RTL simulators, and co-simulation frameworks. Ensuring compatibility and smooth interaction between these tools is essential for a successful implementation.

Case Study: Hybrid Prototyping for an ARM Cortex-A53 SoC

Consider an ARM Cortex-A53-based SoC with a custom GPU and a DDR4 memory controller. The Cortex-A53 cores and memory subsystem are modeled using ARM Fast Models, while the GPU and DDR4 controller are simulated at the RTL level. A transactor bridges the high-level model and RTL simulation, converting AXI transactions between the two domains.

During simulation, the software team develops and tests a graphics driver using the high-level model, while the hardware team verifies the timing and functionality of the GPU and DDR4 controller at the RTL level. The hybrid prototyping environment enables both teams to collaborate effectively, identifying and resolving issues early in the design cycle. For example, a timing violation in the GPU’s AXI interface is detected and debugged using the co-simulation framework, ensuring that the issue is fixed before tape-out.

Conclusion

Hybrid prototyping is a powerful solution for ARM SoC design and verification, combining the speed of high-level models with the accuracy of RTL simulations. By enabling seamless integration of different abstraction levels, hybrid prototyping addresses the challenges of simulation speed, accuracy, and debugging, ultimately reducing development cycles and improving verification coverage. As ARM-based SoCs continue to grow in complexity, hybrid prototyping will play an increasingly important role in ensuring successful design and verification outcomes.