ETM and ETF Configuration Issues in On-Chip Trace Capture
The core issue revolves around the inability to capture execution trace data using the Embedded Trace Macrocell (ETM) and Embedded Trace FIFO (ETF) on the STM32H7 Cortex-M7 microcontroller. The goal is to record every instruction executed by the CPU in a circular buffer mode on-chip, with the trace data being stored in the ETF’s SRAM. However, the ETF FIFO remains empty, and the status bit indicating data availability never raises. This suggests a misconfiguration or improper initialization sequence in the ETM, ETF, or related CoreSight components.
The ETM is responsible for generating trace packets that represent the execution flow of the CPU. These packets are then routed through the Trace Funnel (CSTF) and stored in the ETF’s SRAM. The ETF acts as a buffer, allowing the trace data to be read out later. The Data Watchpoint and Trace (DWT) unit is also involved, though its role in this specific setup is less clear since no filtering is required. The interaction between these components is critical for successful trace capture.
The provided code initializes the ETM, ETF, and DWT registers based on the ARM architecture reference manuals. However, the ETF FIFO remains empty, indicating that either the ETM is not generating trace packets, the packets are not reaching the ETF, or the ETF is not properly configured to store the incoming data. The relationship between the ETM, CSTF, and ETF must be carefully examined to identify the root cause.
Misconfigured ETM Trace ID and ETF Trigger Settings
One of the primary causes of the ETF FIFO remaining empty is the misconfiguration of the ETM Trace ID and ETF trigger settings. The ETM Trace ID is a unique identifier that associates trace packets with a specific source. If the Trace ID is not correctly set, the ETF may not recognize the incoming trace packets, resulting in an empty FIFO. In the provided code, the ETM Trace ID is set to 0xAB, but this value must align with the configuration of the ETF and CSTF.
The ETF trigger settings are also critical. The ETF is configured to capture a specific number of 32-bit words (*ETF_TRG = 16), but the trigger conditions may not be met if the ETM is not generating trace packets or if the packets are not properly synchronized. The ETF’s Formatter and Flush Control Register (*ETF_FFCR) is set to 0x00001123, which enables various features such as stopping on flush and enabling triggers. However, these settings may not be sufficient to ensure that the ETF captures the trace data correctly.
Another potential issue is the initialization sequence of the CoreSight components. The ETM, CSTF, and ETF must be enabled in a specific order to ensure proper communication between them. If the CSTF is not correctly configured to route trace packets from the ETM to the ETF, the FIFO will remain empty. Additionally, the DWT unit is enabled in the code, but its role in this setup is unclear. The DWT is typically used for filtering or triggering trace capture, but since no filtering is required, its configuration may be unnecessary or even interfering with the ETM operation.
Correcting ETM and ETF Configuration for Successful Trace Capture
To resolve the issue of the ETF FIFO remaining empty, the following steps should be taken to ensure proper configuration and initialization of the ETM, CSTF, and ETF:
Step 1: Verify ETM Trace ID and Synchronization
Ensure that the ETM Trace ID (*ETM_TRACEIDR) is correctly set and matches the configuration expected by the ETF. The Trace ID should be unique and consistent across all CoreSight components. Additionally, verify that the ETM synchronization settings (*ETM_SYNCPR) are correctly configured to ensure that trace packets are properly aligned and recognized by the ETF.
Step 2: Reconfigure ETF Trigger and Formatter Settings
Review the ETF trigger settings (*ETF_TRG) and ensure that they align with the expected trace data volume. Adjust the number of 32-bit words to capture based on the available SRAM size and the desired trace depth. Reconfigure the ETF Formatter and Flush Control Register (*ETF_FFCR) to ensure that all necessary features are enabled, such as stopping on flush and enabling triggers. Consider setting the ENFT bit to ensure that the ETF captures trace data even if the trigger condition is not met.
Step 3: Validate CoreSight Component Initialization Sequence
Ensure that the CoreSight components are initialized in the correct order. The recommended sequence is as follows:
- Enable the DWT unit (
*DEMCR |= 1<<24) and configure it if necessary. - Enable the CSTF (
*CSTF_CTRL |= 1) to ensure that the ETM trace packets are routed to the ETF. - Configure and enable the ETM (
*ETM_PRGCTRL |= 1). - Configure and enable the ETF (
*ETF_CTL = 1).
Step 4: Monitor ETF Status and Debug Trace Packet Generation
After enabling the ETF, monitor the ETF status register (*ETF_STS) to check for any errors or warnings. If the FIFO remains empty, verify that the ETM is generating trace packets by checking the ETM status register (*ETM_STAT). If the ETM is not generating packets, review its configuration and ensure that it is properly enabled and synchronized.
Step 5: Implement Debugging and Validation Mechanisms
Add debugging mechanisms to validate the trace data capture process. For example, use a known sequence of instructions (e.g., a loop with __NOP()) and verify that the ETF captures the expected trace packets. Print the contents of the ETF FIFO (*ETF_RRD) to confirm that the trace data is being stored correctly. If necessary, use a logic analyzer or debugger to monitor the trace output pins and verify that the ETM is generating trace packets.
By following these steps, the issue of the ETF FIFO remaining empty can be resolved, enabling successful on-chip trace capture on the STM32H7 Cortex-M7 microcontroller. Proper configuration and initialization of the ETM, CSTF, and ETF are critical to ensuring that trace data is correctly generated, routed, and stored.
