Watchdog Timer Counts Down but HPS Fails to Reboot After Warm Reset
The issue at hand involves the Cyclone V Hard Processor System (HPS) failing to reboot after a watchdog timer triggers a warm reset in a baremetal application. The watchdog timer is configured to count down and initiate a warm reset, but instead of rebooting, the HPS enters a hung or reset state and does not recover. This behavior suggests that the warm reset mechanism is not functioning as expected, preventing the system from reloading the application from the entry point.
The watchdog timer is a critical component in embedded systems, designed to ensure system reliability by resetting the system if the software becomes unresponsive. In this case, the watchdog timer is configured to trigger a warm reset, which should restart the HPS without a full power cycle, allowing the system to resume operation from the application’s entry point. However, the HPS is not recovering after the warm reset, indicating a potential issue with the watchdog configuration, the reset mechanism, or the boot process.
The code provided attempts to configure the watchdog timer (ALT_WDOG1) to trigger a warm reset after a 90-second countdown. The alt_wdog_counter_set function sets the initial counter value, alt_wdog_response_mode_set configures the response mode to warm reset, and alt_wdog_start initiates the watchdog timer. Despite these configurations, the HPS does not reboot as expected, suggesting that the warm reset is either not being triggered correctly or the system is not handling the reset properly.
Misconfigured Watchdog Response Mode or Incomplete Reset Sequence
One possible cause of the issue is a misconfiguration in the watchdog response mode. The alt_wdog_response_mode_set function is used to set the response mode to warm reset, but if this configuration is not applied correctly, the watchdog may not trigger the intended reset behavior. Additionally, the warm reset sequence itself may be incomplete or improperly handled by the HPS, preventing the system from rebooting.
Another potential cause is the interaction between the watchdog timer and the HPS reset controller. The reset controller manages the various reset sources in the HPS, including the watchdog timer. If the reset controller is not configured to handle warm resets from the watchdog timer, the system may not respond correctly to the reset signal. This could result in the HPS entering a hung state instead of rebooting.
The boot process may also be a factor. The HPS is configured to boot from QSPI flash, with the preloader in on-chip RAM and the application in SDRAM. If the warm reset does not properly reinitialize the boot process, the system may fail to reload the application from the entry point. This could be due to incomplete reinitialization of the memory controllers or other critical components during the warm reset.
Verifying Watchdog Configuration and Reset Controller Settings
To troubleshoot the issue, the first step is to verify the watchdog configuration. Ensure that the alt_wdog_response_mode_set function is correctly setting the response mode to warm reset. This can be done by inspecting the watchdog control register after the configuration is applied. The control register should reflect the warm reset setting, indicating that the watchdog is configured to trigger a warm reset upon timeout.
Next, examine the reset controller settings. The reset controller should be configured to handle warm resets from the watchdog timer. This involves checking the reset source enable registers and ensuring that the watchdog timer is listed as a valid reset source. Additionally, verify that the reset controller is configured to properly handle warm resets, including reinitializing the necessary components and restarting the boot process.
The boot process should also be reviewed. Ensure that the warm reset sequence properly reinitializes the memory controllers and other critical components. This may involve checking the boot configuration registers and verifying that the boot process is correctly set up to reload the application from the entry point after a warm reset. If necessary, modify the boot configuration to ensure that the system can recover from a warm reset.
If the watchdog configuration and reset controller settings are correct, the next step is to examine the warm reset sequence itself. This involves analyzing the reset sequence to ensure that all necessary steps are being executed. This may include reinitializing the CPU, memory controllers, and other peripherals, as well as restarting the boot process. If any steps are missing or improperly executed, the system may fail to reboot after a warm reset.
Finally, consider the possibility of a hardware issue. If the watchdog timer or reset controller is not functioning correctly, the system may not respond properly to the warm reset signal. This could be due to a faulty component or an issue with the board design. In this case, further hardware testing may be required to identify and resolve the issue.
By systematically verifying the watchdog configuration, reset controller settings, and boot process, it should be possible to identify the root cause of the warm reset failure and implement the necessary fixes to ensure that the HPS reboots correctly after a watchdog timeout.
