Cortex-M55 Default Address Map and Boot Vector Placement
The Cortex-M55 processor, like other ARM Cortex-M series processors, follows a predefined memory map that dictates how the processor interacts with memory and peripherals. This memory map is crucial for understanding where code, data, and peripherals are located, and it plays a significant role in the boot process. The default address map for the Cortex-M55 specifies that code can be fetched from the address range 0x00000000 to 0x1FFFFFFF. This range is typically associated with the Instruction Tightly Coupled Memory (ITCM) or the Master-AXI (M-AXI) interface.
At reset, the Cortex-M55 processor begins execution by fetching the initial stack pointer (MSP) and the program counter (PC) from the vector table. The vector table is a critical data structure that contains the addresses of exception handlers and the initial stack pointer. The Vector Table Offset Register (VTOR) determines the base address of this vector table. By default, the VTOR is set to 0x00000000, meaning the processor expects the vector table to be located at the start of the address space.
However, the Cortex-M55 provides flexibility in configuring the VTOR through hardware signals. Specifically, the processor has two input signals, INITSVTOR and INITNSVTOR, which are used to set the vector table addresses for Secure and Non-secure states, respectively. These signals are sampled at reset, and their values must be stable during the reset process to ensure correct initialization. The INITSVTOR[31:7] signal, for example, directly influences the address from which the processor loads the MSP and PC values.
The Cortex-M55’s default address map also enforces certain restrictions on where code and vector tables can be placed. Specifically, both the vector table and the code must reside in Normal Memory, as the Peripheral region is marked as eXecute Never (XN). This means that attempting to execute code from the Peripheral region will result in a fault. Therefore, it is essential to ensure that the vector table and the associated code are placed within the valid address ranges defined by the default memory map.
Flexibility and Restrictions in VTOR Configuration
While the Cortex-M55 provides flexibility in configuring the VTOR, there are still restrictions that must be considered. The VTOR can be configured to point to any address within the valid memory ranges, but it must adhere to the constraints imposed by the default address map. The valid address ranges for the VTOR are as follows:
- 0x00000000 – 0x1FFFFFFF
- 0x20000000 – 0x3FFFFFFF
- 0x60000000 – 0x9FFFFFFF
These ranges correspond to the Normal Memory regions in the Cortex-M55’s default address map. It is important to note that the VTOR cannot be configured to point to an address outside these ranges, as doing so would result in the processor attempting to fetch the vector table from an invalid or XN region, leading to a fault.
The ability to configure the VTOR through hardware signals such as INITSVTOR and INITNSVTOR provides a mechanism for customizing the boot process. For example, in a system with multiple memory banks, the VTOR can be configured to point to a specific memory bank at reset, allowing for different boot configurations depending on the system’s requirements. However, this flexibility must be used with caution, as incorrect configuration of the VTOR can lead to unpredictable behavior or system failure.
One common misconception is that the VTOR can be configured to point to any arbitrary address, regardless of the memory map. This is not the case, as the Cortex-M55’s memory map enforces strict boundaries on where code and data can be placed. Attempting to configure the VTOR to point to an address outside the valid ranges will result in the processor being unable to fetch the vector table, leading to a failure in the boot process.
Ensuring Correct VTOR Configuration and Memory Placement
To ensure correct VTOR configuration and memory placement, several steps must be taken. First, the system designer must ensure that the vector table and the associated code are placed within the valid address ranges defined by the Cortex-M55’s default memory map. This can be achieved by carefully configuring the memory layout in the linker script and ensuring that the VTOR is set to the correct base address.
Second, the hardware signals INITSVTOR and INITNSVTOR must be properly configured to reflect the desired vector table addresses. These signals must be stable at reset, as they are sampled by the processor during the initialization process. Any instability in these signals can lead to incorrect VTOR configuration, resulting in a failure to boot.
Third, the system designer must ensure that the memory regions used for the vector table and code are marked as Normal Memory and are not marked as eXecute Never (XN). This can be achieved by configuring the Memory Protection Unit (MPU) or the system’s memory controller to enforce the correct memory attributes.
Finally, it is important to verify the VTOR configuration and memory placement through testing. This can be done by using a debugger to inspect the VTOR and the memory contents at the configured address. Additionally, the system should be tested under various conditions to ensure that the VTOR configuration remains stable and that the processor can successfully fetch the vector table and execute the code.
In summary, the Cortex-M55’s default address map and VTOR configuration provide a flexible mechanism for customizing the boot process, but they also impose strict restrictions on where code and vector tables can be placed. By carefully configuring the VTOR and ensuring that the vector table and code are placed within the valid address ranges, system designers can ensure a successful boot process and reliable operation of the Cortex-M55 processor.
