Cortex-A9 MPCore Interrupt Handling: IRQ Vector Misdirection and Debugging

Cortex-A9 MPCore IRQ Vector Misdirection During Local Timer Interrupt

The Cortex-A9 MPCore processor, when configured to handle interrupts via the Generic Interrupt Controller (GIC), is experiencing a misdirection of the interrupt vector. Specifically, when a local timer interrupt (vector 29) is triggered, the processor incorrectly jumps to the Supervisor Call (SVC) exception handler instead of the intended Interrupt Request (IRQ) handler. This misdirection occurs despite the GIC correctly identifying the local timer interrupt as the highest priority pending interrupt and the IRQ exception being enabled in the CPSR. The issue is further complicated by the fact that the vector table is correctly configured, and the VBAR (Vector Base Address Register) is properly set to point to the exception vector table.

The problem manifests in a bare-metal environment on an i.MX6Quad processor, where the local timer interrupt is configured as a Private Peripheral Interrupt (PPI) targeting core 1. The GIC registers indicate that the interrupt is enabled, pending, and correctly prioritized, yet the processor fails to execute the IRQ handler. Instead, it erroneously branches to the SVC handler, suggesting a potential issue with the exception vector table alignment, VBAR configuration, or the interaction between the GIC and the processor’s exception handling logic.

Misconfigured VBAR, SCTLR.V Bit, or GIC-to-CPU Interface

The root cause of the IRQ vector misdirection can be attributed to one or more of the following factors: an improperly configured VBAR, an incorrect setting of the SCTLR.V bit, or a misalignment in the GIC-to-CPU interface. The VBAR must point to a 4-byte aligned memory location containing the exception vector table, and the SCTLR.V bit must be cleared to ensure the processor uses the VBAR for exception vector addressing. Additionally, the GIC must be correctly configured to forward interrupts to the CPU, and the CPU must be in the correct mode to handle IRQ exceptions.

The VBAR configuration is critical because it determines the base address of the exception vector table. If the VBAR is not set correctly, the processor may use a default vector table, leading to incorrect exception handling. The SCTLR.V bit, when set, forces the processor to use a fixed memory range for exception vectors, overriding the VBAR. If this bit is not cleared, the processor may ignore the VBAR and use the default vector table, resulting in the observed misdirection.

The GIC-to-CPU interface must also be examined. The GIC is responsible for prioritizing and forwarding interrupts to the CPU, and the CPU must acknowledge the interrupt by reading the GICC_IAR register. If the GIC is not correctly configured or if the CPU fails to acknowledge the interrupt, the processor may not handle the interrupt as expected. Furthermore, the CPSR must have the IRQ exception enabled (I bit cleared) to allow the processor to respond to IRQ exceptions.

Correcting VBAR Configuration, SCTLR.V Bit, and GIC-CPU Synchronization

To resolve the IRQ vector misdirection issue, the following steps must be taken to ensure proper configuration of the VBAR, SCTLR.V bit, and GIC-to-CPU interface:

Step 1: Verify VBAR Configuration
The VBAR must be set to the base address of the exception vector table, which must be aligned to a 4-byte boundary. The following assembly code demonstrates how to correctly set the VBAR:

set_vbar
   ldr r0, =vector_tbl       // Load the address of the vector table into r0
   mcr p15, 0, r0, c12, c0, 0 // Write r0 to VBAR

The vector_tbl symbol must be defined at a 4-byte aligned memory location. The alignment can be enforced using the .align directive in assembly or the __attribute__((aligned(4))) in C.

Step 2: Clear the SCTLR.V Bit
The SCTLR.V bit must be cleared to ensure the processor uses the VBAR for exception vector addressing. The following assembly code demonstrates how to clear the SCTLR.V bit:

   mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into r0
   bic r0, r0, #0x2000        // Clear the V bit (bit 13)
   mcr p15, 0, r0, c1, c0, 0 // Write r0 back to SCTLR

Step 3: Verify GIC Configuration
The GIC must be configured to enable and prioritize the local timer interrupt. The following steps outline the necessary GIC configurations:

1. Enable the local timer interrupt in the GICD_ISENABLER0 register.
2. Set the priority of the local timer interrupt in the GICD_PRIORITY29 register.
3. Ensure the local timer interrupt is configured as a non-secure interrupt in the GICD_GROUPR0 register.
4. Enable the GIC distributor by setting the GICD_CTLR register.

Step 4: Ensure Proper GIC-CPU Synchronization
The CPU must acknowledge the interrupt by reading the GICC_IAR register. The following assembly code demonstrates how to acknowledge the interrupt:

irq_isr
   push {r0-r12, lr}          // Save registers
   ldr r0, =GICC_IAR          // Load the address of GICC_IAR into r0
   ldr r1, [r0]               // Read GICC_IAR to acknowledge the interrupt
   // Handle the interrupt
   ldr r0, =irq_hnlr          // Load the address of the IRQ handler
   blx r0                     // Branch to the IRQ handler
   // Signal end of interrupt
   ldr r0, =GICC_EOIR         // Load the address of GICC_EOIR into r0
   str r1, [r0]               // Write the interrupt ID to GICC_EOIR
   pop {r0-r12, lr}           // Restore registers
   subs pc, lr, #4            // Return from exception

Step 5: Verify CPSR Configuration
The CPSR must have the IRQ exception enabled (I bit cleared) to allow the processor to respond to IRQ exceptions. The following assembly code demonstrates how to clear the I bit in the CPSR:

   cpsie i                    // Enable IRQ exceptions

Step 6: Debugging and Validation
To validate the correct handling of the local timer interrupt, set a breakpoint at the first instruction of the IRQ handler and monitor the GIC and CPU registers. Ensure that the GICC_IAR register correctly identifies the local timer interrupt and that the processor branches to the IRQ handler. If the issue persists, verify the alignment of the exception vector table and the correctness of the VBAR and SCTLR.V bit configurations.

By following these steps, the IRQ vector misdirection issue can be resolved, ensuring that the Cortex-A9 MPCore processor correctly handles the local timer interrupt. Proper configuration of the VBAR, SCTLR.V bit, and GIC-to-CPU interface is essential for reliable interrupt handling in bare-metal environments.