ARM Trusted Firmware-A (TF-A) Boot Flow Issues with BL2 at EL3 and Custom BL33 Payloads

BL2 at EL3 Execution Level and Custom BL33 Payload Integration Challenges

The integration of BL2 at EL3 execution level with custom BL33 payloads in ARM Trusted Firmware-A (TF-A) presents a unique set of challenges, particularly when dealing with the i.MX8QM platform. The primary issue revolves around the proper configuration and utilization of the BL2_AT_EL3 build option and the PRELOADED_BL33_BASE parameter to ensure a seamless boot flow. The BL2_AT_EL3 option allows BL2 to execute at EL3, which is typically reserved for secure monitor code, while the PRELOADED_BL33_BASE parameter specifies the memory address where a custom BL33 payload, such as a Linux kernel or an application, is preloaded. The complexity arises from the need to ensure that the boot flow correctly transitions from BL2 at EL3 to the custom BL33 payload without causing memory conflicts or execution errors.

The i.MX8QM platform, which is based on the ARM Cortex-A53 and Cortex-A72 cores, requires careful handling of the boot flow to ensure that the secure and non-secure states are properly managed. The BL2_AT_EL3 option is particularly useful in scenarios where the bootloader needs to perform secure operations before handing control over to the non-secure world. However, the integration of a custom BL33 payload adds another layer of complexity, as the payload must be correctly positioned in memory and the boot flow must be configured to jump to the correct entry point.

Memory Address Configuration and Boot Flow Transition Errors

One of the primary causes of boot flow issues when using BL2_AT_EL3 and custom BL33 payloads is incorrect memory address configuration. The PRELOADED_BL33_BASE parameter must be set to the correct memory address where the custom BL33 payload is loaded. If this address is not correctly specified, the boot flow may attempt to jump to an incorrect memory location, resulting in a segmentation fault or other execution errors. Additionally, the memory region specified by PRELOADED_BL33_BASE must be properly mapped and accessible by the ARM cores during the boot process.

Another potential cause of boot flow issues is the improper handling of the transition from BL2 at EL3 to the custom BL33 payload. The transition must be carefully managed to ensure that the ARM cores are in the correct state (secure or non-secure) and that the necessary registers and memory mappings are properly configured. If the transition is not handled correctly, the system may fail to boot or may exhibit unpredictable behavior.

The i.MX8QM platform also introduces additional complexity due to its multi-core architecture. The boot flow must be configured to correctly initialize all cores and ensure that they are properly synchronized before handing control over to the custom BL33 payload. This requires careful management of the ARM cores’ state and the use of appropriate synchronization mechanisms to ensure that all cores are ready to execute the payload.

Configuring BL2 at EL3 and Custom BL33 Payload for i.MX8QM

To address the challenges associated with using BL2_AT_EL3 and custom BL33 payloads on the i.MX8QM platform, the following steps should be taken:

1. Verify Memory Address Configuration: Ensure that the PRELOADED_BL33_BASE parameter is set to the correct memory address where the custom BL33 payload is loaded. This address must be within a memory region that is accessible by the ARM cores during the boot process. Use the platform’s memory map to verify that the specified address is valid and does not conflict with other memory regions used by the bootloader or the platform’s firmware.

2. Configure BL2 at EL3: Enable the BL2_AT_EL3 build option in the TF-A build configuration. This option allows BL2 to execute at EL3, which is necessary for performing secure operations before transitioning to the non-secure world. Ensure that the build configuration is correctly set up to include all necessary dependencies and that the build process completes without errors.

3. Manage Boot Flow Transition: Carefully manage the transition from BL2 at EL3 to the custom BL33 payload. This involves ensuring that the ARM cores are in the correct state (secure or non-secure) and that the necessary registers and memory mappings are properly configured. Use the appropriate ARM instructions to set the core state and configure the memory mappings before jumping to the custom BL33 payload.

4. Synchronize Multi-Core Initialization: On the i.MX8QM platform, ensure that all ARM cores are properly initialized and synchronized before handing control over to the custom BL33 payload. This may involve using synchronization mechanisms such as spinlocks or barriers to ensure that all cores are ready to execute the payload. The boot flow should be configured to initialize each core individually and then synchronize them before transitioning to the payload.

5. Debug and Validate Boot Flow: Use debugging tools such as JTAG or serial output to monitor the boot flow and identify any issues that may arise during the transition from BL2 at EL3 to the custom BL33 payload. Validate that the payload is correctly executed and that the system boots as expected. If issues are encountered, use the debugging tools to trace the execution flow and identify the root cause of the problem.

6. Optimize Boot Flow Performance: Once the boot flow is correctly configured and validated, consider optimizing the performance of the boot process. This may involve reducing the time spent in BL2 at EL3, optimizing the memory mappings, or improving the synchronization mechanisms used during the transition to the custom BL33 payload. Performance optimization should be done carefully to ensure that it does not introduce new issues or compromise the stability of the boot flow.

By following these steps, the challenges associated with using BL2_AT_EL3 and custom BL33 payloads on the i.MX8QM platform can be effectively addressed, ensuring a smooth and reliable boot flow. The key is to carefully manage the memory address configuration, boot flow transition, and multi-core synchronization to ensure that the system boots correctly and executes the custom payload as expected.