ARM Cortex-A9 PMU Counter Stalls During Data Cache Access Timing Measurements

ARM Cortex-A9 PMU Counter Stalls During Data Cache Access Timing Measurements

The Performance Monitor Unit (PMU) in ARM Cortex-A9 processors is a powerful tool for profiling and analyzing system performance. However, when attempting to measure data cache access times using the PMU, users may encounter unexpected behavior where the PMU counter appears to stall or deliver constant values intermittently. This issue is particularly prevalent when configuring the PMU to monitor specific events, such as data cache accesses (event 0x4), and attempting to read the counter values in real-time. The problem manifests as a discrepancy between the expected incremental behavior of the PMU counter and the observed constant values, followed by sudden increments after a delay. This behavior raises questions about the timing constraints between memory operations (reads/writes) and PMU counter updates, as well as the potential need for manual counter flushing or synchronization.

PMU Counter Update Latency and Event Sampling Constraints

The ARM Cortex-A9 PMU operates by counting specific microarchitectural events, such as cache accesses, branch predictions, or cycle counts. However, the PMU does not update its counters instantaneously. Instead, there is a inherent latency between the occurrence of an event and the reflection of that event in the PMU counter. This latency is influenced by several factors, including the pipeline depth of the Cortex-A9, the event sampling rate, and the interaction between the PMU and the memory system.

When measuring data cache access times, the PMU counter is configured to increment on every data cache access event (event 0x4). However, the Cortex-A9’s pipeline and memory system introduce delays that can cause the PMU counter to appear stalled. For example, if the processor is executing a series of load/store instructions in a loop, the PMU counter may not update immediately after each instruction due to the pipeline’s out-of-order execution and the memory system’s response time. Additionally, the PMU counter may be sampled at a rate that is slower than the frequency of cache accesses, leading to the perception of constant values.

Another factor contributing to the observed behavior is the PMU’s event sampling mechanism. The PMU does not sample events continuously but rather at specific intervals determined by the processor’s clock cycle and the PMU’s configuration. If the sampling interval is longer than the time between consecutive cache accesses, the PMU counter may not reflect every individual access, resulting in apparent stalls.

Furthermore, the Cortex-A9’s memory system includes features such as write buffers and cache line fills, which can delay the visibility of memory operations to the PMU. For instance, a store operation may be buffered before being written to the cache, causing a delay before the corresponding PMU counter increment is registered. Similarly, a cache miss may trigger a cache line fill, during which the PMU counter may not update until the fill is complete.

Implementing PMU Counter Synchronization and Cache Management

To address the issue of PMU counter stalls during data cache access timing measurements, several steps can be taken to ensure accurate and consistent counter updates. These steps involve synchronizing the PMU counter with memory operations, managing the cache to minimize delays, and configuring the PMU for optimal event sampling.

First, it is essential to insert memory synchronization barriers between memory operations and PMU counter reads. The ARM architecture provides Data Synchronization Barriers (DSB) and Data Memory Barriers (DMB) to enforce ordering of memory operations. By inserting a DSB instruction after a series of load/store instructions, the processor ensures that all memory operations are completed before proceeding to read the PMU counter. This synchronization prevents the PMU counter from being read before the corresponding cache accesses have been registered.

Second, cache management techniques can be employed to minimize delays in PMU counter updates. For example, cache invalidation and cleaning operations can be used to ensure that the cache is in a known state before starting the measurement. The DCIMVAC (Data Cache Invalidate by Modified Virtual Address to PoC) and DCCIMVAC (Data Cache Clean by Modified Virtual Address to PoC) instructions can be used to invalidate or clean specific cache lines, respectively. By managing the cache state, the impact of cache line fills and write buffers on PMU counter updates can be reduced.

Third, the PMU configuration should be optimized for the specific measurement scenario. The PMU supports various configuration options, such as event filtering, counter overflow interrupts, and cycle counting. For data cache access timing measurements, it is important to configure the PMU to sample events at a rate that matches the expected frequency of cache accesses. This can be achieved by adjusting the PMU’s sampling interval or by using multiple counters to capture different aspects of cache behavior.

Additionally, the PMU counter can be manually flushed to ensure that it reflects the most recent events. The PMXEVCNTR register can be written to reset the counter to a specific value, effectively flushing any pending updates. This manual flushing can be performed after a series of memory operations to ensure that the counter reflects the cumulative effect of those operations.

Finally, it is important to consider the impact of processor frequency scaling and power management on PMU counter updates. The Cortex-A9 processor may dynamically adjust its clock frequency or enter low-power states, which can affect the timing of PMU counter updates. To ensure consistent measurements, the processor should be configured to operate at a fixed frequency, and power management features should be disabled during the measurement period.

By implementing these synchronization and cache management techniques, the issue of PMU counter stalls during data cache access timing measurements can be effectively addressed. The resulting measurements will be more accurate and consistent, providing valuable insights into the performance of the Cortex-A9’s memory system.

Detailed Troubleshooting Steps for PMU Counter Stalls

To systematically troubleshoot and resolve the issue of PMU counter stalls during data cache access timing measurements, follow these detailed steps:

1. Verify PMU Configuration: Ensure that the PMU is correctly configured to monitor the desired event (e.g., data cache accesses, event 0x4). Check the PMCR (Performance Monitor Control Register) and PMSELR (Performance Monitor Event Counter Selection Register) to confirm that the event is enabled and assigned to the appropriate counter.

2. Insert Memory Synchronization Barriers: After performing a series of load/store instructions, insert a Data Synchronization Barrier (DSB) to ensure that all memory operations are completed before reading the PMU counter. This prevents the counter from being read before the corresponding cache accesses have been registered.

3. Manage Cache State: Use cache invalidation and cleaning instructions to ensure that the cache is in a known state before starting the measurement. For example, use DCIMVAC to invalidate specific cache lines or DCCIMVAC to clean modified cache lines. This minimizes delays caused by cache line fills and write buffers.

4. Optimize PMU Sampling Interval: Adjust the PMU’s sampling interval to match the expected frequency of cache accesses. If the sampling interval is too long, the PMU counter may not reflect every individual access, leading to apparent stalls. Experiment with different sampling intervals to find the optimal configuration.

5. Manually Flush PMU Counter: After a series of memory operations, manually flush the PMU counter by writing to the PMXEVCNTR register. This ensures that the counter reflects the cumulative effect of the operations and eliminates any pending updates.

6. Disable Frequency Scaling and Power Management: Configure the processor to operate at a fixed frequency and disable power management features during the measurement period. This prevents variations in PMU counter updates caused by dynamic frequency scaling or low-power states.

7. Monitor Counter Overflow: If the PMU counter overflows during the measurement, it may appear to stall or reset. Enable counter overflow interrupts or use multiple counters to handle large event counts without losing accuracy.

8. Validate Measurement Results: Compare the PMU counter values with expected results based on the number of cache accesses and the known latency of the memory system. If discrepancies persist, revisit the PMU configuration and synchronization steps to identify potential issues.

By following these troubleshooting steps, the issue of PMU counter stalls during data cache access timing measurements can be systematically resolved. The resulting measurements will provide accurate and reliable insights into the performance of the ARM Cortex-A9’s memory system, enabling effective optimization and debugging of embedded applications.