ARM Cortex-A78 DC ZVA Instruction Alignment Fault During Linux Kernel Boot
DC ZVA Instruction Execution Failure in __pi_memset Function
The ARM Cortex-A78 processor is encountering an alignment fault when executing the DC ZVA (Data Cache Zero by VA) instruction within the __pi_memset function during the Linux kernel boot process. The __pi_memset function is part of the __primary_switched function located in the head.S file of the Linux kernel. The alignment fault is indicative of the memory region being accessed by the DC ZVA instruction being marked as "Device Type" memory rather than "Normal Memory." This is problematic because the DC ZVA instruction is designed to operate on Normal Memory, and attempting to execute it on Device Memory results in an alignment fault.
The ARMv8-A architecture specifies that the DC ZVA instruction is used to zero a block of memory in the cache. This instruction is particularly useful during the initialization phase of the kernel, where large blocks of memory need to be zeroed out efficiently. However, the instruction is only valid for Normal Memory regions. If the memory type is incorrectly configured as Device Memory, the processor will raise an alignment fault.
In this scenario, the MAIR_EL1 (Memory Attribute Indirection Register) has been configured to indicate Normal Memory attributes, but the PAR_EL1 (Physical Address Register) reveals that the memory region being accessed by the DC ZVA instruction is still being treated as Device Memory. This discrepancy suggests that the memory type configuration in the MMU (Memory Management Unit) or the page tables is not correctly reflecting the intended memory attributes.
Misconfigured Memory Attributes and HCR_EL2.TDZ Bit
The root cause of the alignment fault lies in the misconfiguration of memory attributes, specifically the memory type being incorrectly set as Device Memory instead of Normal Memory. The MAIR_EL1 register is responsible for defining memory attributes, and in this case, it has been correctly set to indicate Normal Memory. However, the PAR_EL1 register, which provides the physical address and memory attributes resulting from a translation table walk, indicates that the memory region is still being treated as Device Memory.
One possible cause of this misconfiguration is the HCR_EL2.TDZ (Trap DC ZVA) bit in the Hypervisor Configuration Register. The HCR_EL2.TDZ bit controls whether the DC ZVA instruction is trapped when executed in EL1 (Exception Level 1). If the HCR_EL2.TDZ bit is set to 1, the DC ZVA instruction will be trapped and handled by the hypervisor, potentially leading to unexpected behavior. However, in this case, the HCR_EL2.TDZ bit is confirmed to be set to 0, indicating that the DC ZVA instruction should not be trapped.
Another potential cause is the SCTLR_EL1.DZE (DC ZVA Enable) bit in the System Control Register. The SCTLR_EL1.DZE bit controls whether the DC ZVA instruction is enabled at EL1. In this scenario, the SCTLR_EL1.DZE bit is set to 1, indicating that the DC ZVA instruction is enabled and should execute without trapping.
Given that both the HCR_EL2.TDZ and SCTLR_EL1.DZE bits are correctly configured, the issue likely stems from an incorrect memory type configuration in the MMU or page tables. The memory type is determined by the attributes specified in the translation tables, and if these attributes are not correctly set to Normal Memory, the DC ZVA instruction will fail with an alignment fault.
Correcting Memory Type Configuration and Ensuring Proper Cache Management
To resolve the alignment fault caused by the DC ZVA instruction, the memory type configuration must be corrected to ensure that the memory region being accessed is marked as Normal Memory. This involves verifying and updating the memory attributes in the MMU and page tables.
First, the translation tables used by the MMU must be examined to ensure that the memory region being accessed by the DC ZVA instruction is correctly marked as Normal Memory. The memory attributes in the translation tables should match those specified in the MAIR_EL1 register. If the memory attributes in the translation tables are incorrect, they must be updated to reflect the correct memory type.
Next, the cache management settings must be verified to ensure that the DC ZVA instruction can execute correctly. This includes checking the cacheability and shareability attributes of the memory region. The memory region should be marked as cacheable and shareable to allow the DC ZVA instruction to operate correctly.
Additionally, the memory barriers and cache maintenance operations must be properly implemented to ensure that the memory attributes are correctly applied and that the cache is in a consistent state. This may involve executing Data Synchronization Barriers (DSB) and Instruction Synchronization Barriers (ISB) to ensure that the memory attributes are correctly propagated and that the cache is properly invalidated or cleaned as needed.
Finally, the system should be tested to ensure that the DC ZVA instruction executes without raising an alignment fault. This may involve running a series of tests to verify that the memory region is correctly marked as Normal Memory and that the DC ZVA instruction operates as expected.
In summary, the alignment fault caused by the DC ZVA instruction on the ARM Cortex-A78 processor is due to a misconfiguration of memory attributes, specifically the memory type being incorrectly set as Device Memory instead of Normal Memory. By correcting the memory type configuration in the MMU and page tables, ensuring proper cache management, and verifying the system settings, the issue can be resolved, allowing the DC ZVA instruction to execute correctly during the Linux kernel boot process.
