ARM Trusted Firmware Bootloader Setup for Cortex-A53 Without U-Boot
The process of configuring the ARM Trusted Firmware (ATF) as a bootloader for the Cortex-A53 processor on the i.MX8QM EVK involves several critical steps. The primary goal is to boot the system using only the ATF (specifically the BL31 binary) without relying on U-Boot. This setup requires a deep understanding of the ARMv8-A architecture, the boot sequence, and the memory mapping of the i.MX8QM platform.
The boot sequence begins with the System Control Firmware (SCFW) and the AHAB container image, which initialize the hardware and prepare the system for the ATF. The BL31 binary is then loaded, which acts as the EL3 runtime firmware. The BL31 binary is responsible for initializing the ARM GICv3, setting up the non-secure memory partitions, and preparing the system for the transition to the normal world (EL2 or EL1).
The debug console output provided in the discussion shows the memory regions being mapped and the successful initialization of the GICv3. The key point of interest is the "Entry point address" displayed as 0x80020000. This address is crucial as it indicates the location in memory where the next stage of the boot process (or the application) will begin execution. Understanding this address and how to configure it is essential for booting secondary bootloaders or applications on the Cortex-A53 cores.
Entry Point Address and Multi-Core Boot Process
The entry point address is the first instruction address of the next loaded image after BL31. In this context, it is set to 0x80020000, which suggests that the next stage of the boot process or the application is expected to be loaded at this address. This address is typically defined in the platform-specific configuration files of the ATF. For the i.MX8QM, this configuration is likely found in the platform’s porting layer within the ATF source code.
The entry point address is critical for multi-core booting. In a multi-core system, the primary core (Core 0) executes the initial boot sequence, including loading the ATF and setting up the memory partitions. Once the primary core has completed its initialization, it can start the secondary cores (Core 1, Core 2, etc.) by jumping to the entry point address. Each secondary core will begin execution at this address, allowing them to run the same or different code as the primary core.
The ATF provides mechanisms for multi-core booting, including the plat_secondary_cold_boot_setup function, which is responsible for setting up the secondary cores. This function is typically implemented in the platform-specific code and is called by the primary core during the boot process. The secondary cores are held in a wait state until the primary core releases them, at which point they begin execution at the entry point address.
Implementing Multi-Core Boot with ARM Trusted Firmware
To implement multi-core booting using the ARM Trusted Firmware, several steps must be followed. First, the entry point address must be correctly configured in the ATF platform-specific code. This address should point to the location in memory where the secondary bootloader or application is loaded. The ATF provides a mechanism for specifying this address through the bl31_plat_get_next_image_ep_info function, which returns the entry point information for the next image.
Once the entry point address is configured, the primary core must initialize the secondary cores. This is done by setting up the necessary registers and memory mappings for the secondary cores and then releasing them from their wait state. The ATF provides the plat_secondary_cold_boot_setup function for this purpose, which should be implemented in the platform-specific code.
The secondary cores will then begin execution at the entry point address, where they can either run the same code as the primary core or branch to a different location to execute their own code. The ATF also provides mechanisms for synchronizing the cores and ensuring that they do not conflict with each other during the boot process.
In addition to the entry point address, the ATF also requires that the memory regions used by the secondary cores be properly configured. This includes setting up the non-secure memory partitions and ensuring that the secondary cores have access to the necessary resources. The ATF provides the bl31_plat_configure_mmu_el3 function for configuring the memory management unit (MMU) for the secondary cores.
Finally, the ATF provides a mechanism for passing control from the primary core to the secondary cores. This is done through the bl31_warm_entrypoint function, which is called by the primary core to start the secondary cores. This function sets up the necessary registers and memory mappings for the secondary cores and then jumps to the entry point address to begin execution.
In summary, booting the Cortex-A53 cores using the ARM Trusted Firmware without U-Boot requires careful configuration of the entry point address, proper initialization of the secondary cores, and correct setup of the memory regions. The ATF provides the necessary mechanisms for implementing multi-core booting, but these must be correctly implemented in the platform-specific code to ensure a successful boot process.
Troubleshooting Multi-Core Boot Issues with ARM Trusted Firmware
When implementing multi-core booting with the ARM Trusted Firmware, several issues can arise that may prevent the secondary cores from starting correctly. One common issue is an incorrect entry point address, which can cause the secondary cores to jump to the wrong location in memory and fail to execute the intended code. This can be resolved by verifying the entry point address in the ATF platform-specific code and ensuring that it points to the correct location in memory.
Another common issue is improper initialization of the secondary cores, which can result in the cores being held in a wait state indefinitely. This can be caused by incorrect configuration of the registers or memory mappings for the secondary cores. To resolve this issue, the plat_secondary_cold_boot_setup function should be carefully reviewed to ensure that the secondary cores are properly initialized and released from their wait state.
Memory region configuration is another potential source of issues. If the memory regions used by the secondary cores are not properly configured, the cores may not have access to the necessary resources, leading to boot failures. This can be resolved by reviewing the bl31_plat_configure_mmu_el3 function and ensuring that the memory regions are correctly set up for the secondary cores.
Finally, synchronization issues between the primary and secondary cores can also cause problems during the boot process. If the primary core does not properly pass control to the secondary cores, they may not start correctly. This can be resolved by reviewing the bl31_warm_entrypoint function and ensuring that the primary core correctly sets up the necessary registers and memory mappings for the secondary cores before jumping to the entry point address.
In conclusion, troubleshooting multi-core boot issues with the ARM Trusted Firmware requires a thorough understanding of the boot process, careful review of the platform-specific code, and attention to detail when configuring the entry point address, initializing the secondary cores, and setting up the memory regions. By following these steps, it is possible to successfully boot the Cortex-A53 cores using the ARM Trusted Firmware without relying on U-Boot.
