CMN-700 SLC Double-Bit ECC Error Injection Mechanism Overview
The ARM CMN-700 (Coherent Mesh Network) is a highly scalable interconnect designed for high-performance systems, particularly in server and infrastructure applications. One of its critical features is the ability to inject errors into the system for testing and validation purposes, such as simulating Single-Level Cell (SLC) double-bit ECC (Error-Correcting Code) errors. The CMN-700 provides a dedicated register, cmn_hns_err_inj, to facilitate error injection. This register allows developers to specify the source and target nodes for error injection, enabling the simulation of fault conditions in the system.
In the described scenario, the goal is to inject a double-bit ECC error into the SLC of a Home Node (HN-F) with Local ID (LID) 0, using a Request Node (RN-SAM) with LID 0 as the source. The process involves configuring the cmn_hns_err_inj register with the appropriate source and target identifiers, followed by accessing memory mapped to the RN-SAM to trigger the error. However, the expected RAS (Reliability, Availability, and Serviceability) interrupt is not generated, indicating a failure in the error injection process.
The CMN-700 architecture relies on a mesh network of interconnected nodes, each with specific roles such as Home Nodes (HN), Request Nodes (RN), and System Address Map (SAM) nodes. The HN-F is responsible for managing cache coherency and memory access, while the RN-SAM acts as a bridge between the processor and the mesh network. The cmn_hns_err_inj register is part of the HN-F’s error injection mechanism, allowing developers to simulate errors by specifying the source and target nodes.
To understand the failure, it is essential to delve into the specifics of the CMN-700 error injection mechanism. The cmn_hns_err_inj register is a 32-bit register with fields for specifying the source node (SrcID), the local port ID (LPID), and the type of error to be injected. In this case, the register is configured with a value of 0x008c0001, where SrcID = 140 and LPID = 0. This configuration is intended to inject a double-bit ECC error into the SLC of the HN-F with LID 0, using the RN-SAM with LID 0 as the source.
The error injection process involves several steps. First, the cmn_hns_err_inj register is configured with the appropriate values. Next, the system accesses memory mapped to the RN-SAM, which should trigger the error injection. If successful, the CMN-700 should generate a RAS interrupt, indicating that the error has been detected and handled by the system. However, in this case, the RAS interrupt is not generated, suggesting that the error injection process has failed.
Misconfiguration of Source and Target Nodes in CMN-700 Error Injection
One of the primary reasons for the failure of the error injection process is the misconfiguration of the source and target nodes in the cmn_hns_err_inj register. The CMN-700 architecture requires precise configuration of the source and target nodes to ensure that the error is injected correctly. In this scenario, the cmn_hns_err_inj register is configured with SrcID = 140 and LPID = 0. However, the relationship between the source and target nodes may not be correctly established, leading to the failure of the error injection process.
The SrcID field in the cmn_hns_err_inj register specifies the source node for the error injection. In this case, the source node is the RN-SAM with LID 0. However, the value 140 for SrcID may not correspond to the correct identifier for the RN-SAM. The CMN-700 architecture assigns unique identifiers to each node in the mesh network, and these identifiers must be correctly specified in the cmn_hns_err_inj register. If the SrcID does not match the actual identifier of the RN-SAM, the error injection process will fail.
Similarly, the LPID field in the cmn_hns_err_inj register specifies the local port ID of the target node. In this case, the target node is the HN-F with LID 0. However, the LPID value of 0 may not correspond to the correct local port ID for the HN-F. The CMN-700 architecture requires that the local port ID be correctly specified to ensure that the error is injected into the correct node. If the LPID does not match the actual local port ID of the HN-F, the error injection process will fail.
Another potential issue is the timing of the error injection. The cmn_hns_err_inj register is configured before the BL1 (Boot Loader Stage 1) booting process. However, the error injection may not be triggered until the system accesses memory mapped to the RN-SAM. If the timing of the error injection is not synchronized with the memory access, the error may not be injected correctly, leading to the failure of the RAS interrupt generation.
Additionally, the CMN-700 architecture includes mechanisms for handling errors, such as the RAS interrupt generation. However, these mechanisms may not be correctly configured or enabled, leading to the failure of the error injection process. The CMN-700 requires that the RAS interrupt generation be enabled and configured correctly to ensure that errors are detected and handled by the system. If the RAS interrupt generation is not enabled or configured correctly, the error injection process will fail.
Correct Configuration and Synchronization of CMN-700 Error Injection
To resolve the issue of failed error injection in the CMN-700, it is essential to ensure that the source and target nodes are correctly configured and that the error injection process is synchronized with the memory access. The following steps outline the correct configuration and synchronization of the CMN-700 error injection process.
First, verify the correct identification of the source and target nodes. The SrcID field in the cmn_hns_err_inj register must correspond to the actual identifier of the RN-SAM. Similarly, the LPID field must correspond to the actual local port ID of the HN-F. This can be achieved by consulting the CMN-700 Technical Reference Manual and the system’s configuration files to ensure that the correct identifiers are used.
Next, ensure that the cmn_hns_err_inj register is configured correctly. The register should be configured with the appropriate values for SrcID and LPID, as well as the type of error to be injected. In this case, the register should be configured to inject a double-bit ECC error into the SLC of the HN-F with LID 0, using the RN-SAM with LID 0 as the source.
Once the cmn_hns_err_inj register is configured correctly, the system should access memory mapped to the RN-SAM to trigger the error injection. This memory access should be synchronized with the error injection process to ensure that the error is injected correctly. The timing of the memory access should be carefully controlled to ensure that it occurs after the cmn_hns_err_inj register is configured but before the system proceeds with other operations.
Additionally, ensure that the RAS interrupt generation is enabled and configured correctly. The CMN-700 architecture includes mechanisms for handling errors, such as the RAS interrupt generation. These mechanisms must be enabled and configured correctly to ensure that errors are detected and handled by the system. This can be achieved by consulting the CMN-700 Technical Reference Manual and the system’s configuration files to ensure that the RAS interrupt generation is enabled and configured correctly.
Finally, verify that the error injection process is successful by monitoring the system for the generation of the RAS interrupt. If the RAS interrupt is generated, the error injection process is successful. If the RAS interrupt is not generated, further investigation is required to identify and resolve any issues with the error injection process.
In conclusion, the failure of the CMN-700 SLC double-bit ECC error injection process is likely due to the misconfiguration of the source and target nodes in the cmn_hns_err_inj register, as well as issues with the timing of the error injection and the configuration of the RAS interrupt generation. By ensuring that the source and target nodes are correctly configured, that the error injection process is synchronized with the memory access, and that the RAS interrupt generation is enabled and configured correctly, the error injection process can be successfully executed.
