ARM Cortex-M0 PRIMASK Interrupt Disabling and Systick Behavior

PRIMASK Bit Set but Systick Interrupts Persist

The issue revolves around the ARM Cortex-M0 processor’s PRIMASK register, which is intended to disable all interrupts except for Non-Maskable Interrupts (NMIs). The user successfully sets the PRIMASK bit to 1 using the __set_PRIMASK(1) function, which is confirmed by reading the PRIMASK value using __get_PRIMASK(). However, despite the PRIMASK bit being set, the Systick timer continues to count down and set the COUNTFLAG in the SYST_CVR (Systick Current Value Register). This behavior is unexpected because the PRIMASK bit should disable all interrupts, including the Systick interrupt.

The Systick timer is a core peripheral in ARM Cortex-M processors, often used for operating system tick generation or timekeeping. It generates an interrupt when the counter reaches zero, which is indicated by the COUNTFLAG in the SYST_CSR (Systick Control and Status Register). The fact that the COUNTFLAG is still being set suggests that the Systick interrupt is not being fully disabled by the PRIMASK bit, which contradicts the expected behavior of the PRIMASK register.

This issue is critical because it affects the deterministic behavior of the system during critical sections of code where interrupts must be disabled to ensure accurate timing or data integrity. If the Systick interrupt is not disabled, it could lead to unexpected context switches or timing inaccuracies, which are particularly problematic in real-time systems.

PRIMASK Scope and Systick Timer Configuration

The root cause of this issue lies in the interaction between the PRIMASK register and the Systick timer’s configuration. The PRIMASK register is designed to disable all interrupts except for NMIs, but the Systick timer’s behavior is influenced by additional factors that may not be immediately apparent.

First, the Systick timer can operate in two modes: polling mode and interrupt mode. In polling mode, the COUNTFLAG is set when the counter reaches zero, but no interrupt is generated. In interrupt mode, the COUNTFLAG triggers an interrupt. The user’s issue suggests that the Systick timer is operating in interrupt mode, but the interrupt is not being masked by the PRIMASK bit.

Second, the Systick timer’s control register (SYST_CSR) has a bit called TICKINT (Systick Interrupt Enable). When TICKINT is set to 1, the Systick timer generates an interrupt when the counter reaches zero. If TICKINT is set to 0, the timer operates in polling mode, and no interrupt is generated. The user’s issue indicates that TICKINT is likely set to 1, allowing the Systick timer to generate interrupts even when PRIMASK is set.

Third, the PRIMASK register only affects the CPU’s ability to respond to interrupts. It does not disable the generation of interrupts by peripherals. This means that even if PRIMASK is set, the Systick timer can still set the COUNTFLAG and generate an interrupt request. The interrupt request will remain pending until PRIMASK is cleared, at which point the CPU will service the interrupt.

Finally, the user’s attempt to write to the CTRL_PRI register to set the PRIMASK bit is incorrect. The PRIMASK bit is part of the CPU’s special-purpose registers and cannot be modified by writing to a peripheral register like CTRL_PRI. This misunderstanding may have contributed to the initial confusion.

Disabling Systick Interrupts via TICKINT and PRIMASK

To resolve the issue, the user must ensure that the Systick timer is properly configured and that the PRIMASK register is used correctly. The following steps outline the necessary actions to disable Systick interrupts effectively:

1. Verify Systick Timer Configuration: Check the SYST_CSR register to confirm the value of the TICKINT bit. If TICKINT is set to 1, the Systick timer is configured to generate interrupts. To disable Systick interrupts, clear the TICKINT bit by writing 0 to it. This can be done using the following code:

   SYST_CSR &= ~(1 << 1); // Clear TICKINT bit
   

   This will prevent the Systick timer from generating interrupts, regardless of the PRIMASK setting.

2. Use PRIMASK Correctly: Ensure that the PRIMASK register is set correctly using the __set_PRIMASK(1) function. This will disable all interrupts except for NMIs. However, note that PRIMASK does not prevent peripherals from generating interrupt requests; it only prevents the CPU from responding to them. Therefore, clearing the TICKINT bit is necessary to fully disable Systick interrupts.

3. Check for Pending Interrupts: After setting PRIMASK and clearing TICKINT, check the NVIC (Nested Vectored Interrupt Controller) to ensure that no Systick interrupt requests are pending. If a Systick interrupt request is pending, it will be serviced as soon as PRIMASK is cleared. To clear any pending Systick interrupt, use the following code:

   NVIC_ClearPendingIRQ(SysTick_IRQn); // Clear pending Systick interrupt
   

4. Re-enable Interrupts: When the critical section of code is complete, re-enable interrupts by clearing the PRIMASK bit using __set_PRIMASK(0). If TICKINT was cleared earlier, it can be re-enabled if needed:

   SYST_CSR |= (1 << 1); // Set TICKINT bit
   __set_PRIMASK(0); // Clear PRIMASK bit
   

5. Verify System Behavior: After making these changes, verify that the Systick timer no longer generates interrupts when PRIMASK is set. This can be done by monitoring the COUNTFLAG in the SYST_CSR register and ensuring that no Systick interrupts are serviced during the critical section of code.

By following these steps, the user can ensure that the Systick timer does not interfere with the critical section of code, even when PRIMASK is set. This approach provides a robust solution to the issue and ensures deterministic behavior in the system.

Additional Considerations for System-Level Integration

While the above steps address the immediate issue, there are additional considerations for system-level integration that can help prevent similar issues in the future:

1. System Initialization: Ensure that the Systick timer and other peripherals are properly initialized during system startup. This includes configuring the SYST_CSR register and setting the TICKINT bit appropriately based on the application’s requirements.

2. Interrupt Prioritization: Use the NVIC to prioritize interrupts and ensure that critical interrupts are handled appropriately. The PRIMASK register should be used sparingly and only for short critical sections to avoid impacting the system’s responsiveness.

3. Debugging and Verification: Use debugging tools to monitor the state of the PRIMASK register, SYST_CSR register, and NVIC during runtime. This can help identify any unexpected behavior and ensure that the system is functioning as intended.

4. Documentation and Code Reviews: Document the use of PRIMASK and other interrupt control mechanisms in the codebase. Conduct code reviews to ensure that these mechanisms are used correctly and consistently across the project.

By addressing these considerations, the user can build a more robust and reliable system that avoids issues related to interrupt handling and timing.