Optimizing C Code for Thumb-1 Instruction Set on Cortex-M0+

ARM Cortex-M0+ DCT32 Fixed-Point MP3 Decoder Performance Bottlenecks

The ARM Cortex-M0+ processor, based on the Thumb-1 instruction set, is widely used in embedded systems due to its low power consumption and cost-effectiveness. However, its limited instruction set and lack of hardware floating-point support make it challenging to optimize performance-critical algorithms, such as the Discrete Cosine Transform (DCT) used in MP3 decoding. The DCT32 function, a key component of MP3 decoding, involves numerous arithmetic operations and memory accesses, which can lead to significant performance bottlenecks if not carefully optimized.

In the provided code, the DCT32 function is implemented using fixed-point arithmetic to avoid the overhead of floating-point operations. The function processes a buffer of 32-bit integers, performing a series of additions, subtractions, and multiplications. The code is structured to minimize the use of the stack frame, which is crucial for reducing memory access latency on the Cortex-M0+. However, the current implementation still has room for improvement in terms of instruction selection, register usage, and memory access patterns.

The primary performance bottlenecks in the DCT32 function stem from the following issues:

1. Inefficient Use of Registers: The Cortex-M0+ has only 13 general-purpose registers (R0-R12), with R13 (SP) reserved for the stack pointer. The current implementation uses a large number of intermediate variables, which forces the compiler to spill registers to the stack, increasing memory access latency.

2. Suboptimal Memory Access Patterns: The code accesses the buffer and coefficient pointers multiple times within the loop, leading to redundant memory loads and stores. This not only increases the number of memory accesses but also prevents the compiler from optimizing the memory access patterns.

3. Lack of Instruction-Level Parallelism: The Thumb-1 instruction set has limited support for parallel execution of instructions. The current implementation does not take full advantage of the available instruction-level parallelism, leading to suboptimal utilization of the processor’s execution units.

4. Inefficient Use of Addressing Modes: The Cortex-M0+ supports several addressing modes, including base-plus-offset and base-plus-index, which can be used to optimize memory access. However, the current implementation does not fully exploit these addressing modes, leading to additional instructions and cycles being spent on address calculations.

Register Spillage and Memory Access Latency in Fixed-Point Arithmetic

The Cortex-M0+ processor’s limited register set and simple instruction set make it particularly sensitive to register spillage and memory access latency. In the DCT32 function, the use of a large number of intermediate variables forces the compiler to spill registers to the stack, which significantly impacts performance. Each spill to the stack involves a store operation, followed by a load operation when the value is needed again, adding unnecessary memory access latency.

The fixed-point arithmetic operations in the DCT32 function also contribute to the performance bottlenecks. The MULSHIFT32 macro, which performs a multiplication followed by a right shift, is used extensively in the code. While this macro is necessary for fixed-point arithmetic, its implementation can be optimized to reduce the number of instructions and cycles required. The current implementation of the macro involves multiple memory accesses and arithmetic operations, which can be streamlined to improve performance.

The memory access patterns in the DCT32 function are another source of inefficiency. The code accesses the buffer and coefficient pointers multiple times within the loop, leading to redundant memory loads and stores. This not only increases the number of memory accesses but also prevents the compiler from optimizing the memory access patterns. By reorganizing the code to minimize redundant memory accesses, the performance of the DCT32 function can be significantly improved.

Implementing Register Optimization and Memory Access Pattern Improvements

To address the performance bottlenecks in the DCT32 function, several optimizations can be implemented:

1. Register Optimization: The number of intermediate variables used in the DCT32 function should be minimized to reduce register spillage. This can be achieved by reusing registers for multiple variables and by carefully managing the lifetime of each variable. The use of the stack pointer (R13) as an additional address register can also help reduce register pressure, as it allows for more efficient memory access patterns.

2. Memory Access Pattern Optimization: The memory access patterns in the DCT32 function should be optimized to minimize redundant memory loads and stores. This can be achieved by reorganizing the code to access the buffer and coefficient pointers only once within the loop. The use of base-plus-offset and base-plus-index addressing modes can also help reduce the number of instructions required for address calculations.

3. Instruction-Level Parallelism: The Thumb-1 instruction set has limited support for parallel execution of instructions, but some degree of instruction-level parallelism can still be achieved by carefully scheduling instructions. The DCT32 function should be reorganized to maximize the overlap of arithmetic operations and memory accesses, reducing the overall number of cycles required to execute the function.

4. Fixed-Point Arithmetic Optimization: The MULSHIFT32 macro should be optimized to reduce the number of instructions and cycles required for fixed-point arithmetic. This can be achieved by combining the multiplication and shift operations into a single instruction, where possible, and by minimizing the number of memory accesses required for each operation.

Detailed Optimization Steps

1. Register Allocation and Reuse: The first step in optimizing the DCT32 function is to carefully allocate and reuse registers to minimize spillage. The following table shows the recommended register allocation for the DCT32 function:

Register	Variable	Description
R0	buf	Pointer to the input buffer
R1	cptr	Pointer to the coefficient table
R2	a0	Temporary variable for DCT calculation
R3	a1	Temporary variable for DCT calculation
R4	a2	Temporary variable for DCT calculation
R5	a3	Temporary variable for DCT calculation
R6	a4	Temporary variable for DCT calculation
R7	a5	Temporary variable for DCT calculation
R8	a6	Temporary variable for DCT calculation
R9	a7	Temporary variable for DCT calculation
R10	b0	Temporary variable for DCT calculation
R11	b1	Temporary variable for DCT calculation
R12	b2	Temporary variable for DCT calculation
R13	SP	Stack pointer (used for memory access)

By carefully managing the lifetime of each variable and reusing registers where possible, the number of register spills can be minimized, reducing memory access latency.

2. Memory Access Pattern Reorganization: The memory access patterns in the DCT32 function should be reorganized to minimize redundant memory loads and stores. The following code snippet shows an optimized version of the DCT32 function with improved memory access patterns:

for (i = 4; i > 0; i--) {
    // Load all required values from the buffer in one go
    a0 = *buf++; a7 = *buf++; a3 = *buf++; a4 = *buf++;
    a1 = *buf++; a6 = *buf++; a2 = *buf++; a5 = *buf++;

    // Perform DCT calculations
    b0 = a0 + a7; b7 = MULSHIFT32(*cptr++, a0 - a7) << 1;
    b3 = a3 + a4; b4 = MULSHIFT32(*cptr++, a3 - a4) << 3;
    a0 = b0 + b3; a3 = MULSHIFT32(*cptr, b0 - b3) << 1;
    a4 = b4 + b7; a7 = MULSHIFT32(*cptr++, b7 - b4) << 1;

    b1 = a1 + a6; b6 = MULSHIFT32(*cptr++, a1 - a6) << 1;
    b2 = a2 + a5; b5 = MULSHIFT32(*cptr++, a2 - a5) << 1;
    a1 = b1 + b2; a2 = MULSHIFT32(*cptr, b1 - b2) << 2;
    a5 = b5 + b6; a6 = MULSHIFT32(*cptr++, b6 - b5) << 2;

    // Store results back to the buffer
    *--buf = b0; *--buf = b1; *--buf = b2 + b3; *--buf = b3;
    *--buf = b4 + b6; *--buf = b5 + b7; *--buf = b5 + b6; *--buf = b7;
}

By loading all required values from the buffer in one go and storing the results back to the buffer at the end of the loop, the number of memory accesses is significantly reduced, improving performance.

3. Instruction Scheduling for Parallelism: The Thumb-1 instruction set has limited support for parallel execution, but some degree of instruction-level parallelism can still be achieved by carefully scheduling instructions. The following code snippet shows an optimized version of the DCT32 function with improved instruction scheduling:

for (i = 4; i > 0; i--) {
    // Load all required values from the buffer in one go
    a0 = *buf++; a7 = *buf++; a3 = *buf++; a4 = *buf++;
    a1 = *buf++; a6 = *buf++; a2 = *buf++; a5 = *buf++;

    // Perform DCT calculations with instruction scheduling
    b0 = a0 + a7; b7 = MULSHIFT32(*cptr++, a0 - a7) << 1;
    b3 = a3 + a4; b4 = MULSHIFT32(*cptr++, a3 - a4) << 3;
    a0 = b0 + b3; a3 = MULSHIFT32(*cptr, b0 - b3) << 1;
    a4 = b4 + b7; a7 = MULSHIFT32(*cptr++, b7 - b4) << 1;

    b1 = a1 + a6; b6 = MULSHIFT32(*cptr++, a1 - a6) << 1;
    b2 = a2 + a5; b5 = MULSHIFT32(*cptr++, a2 - a5) << 1;
    a1 = b1 + b2; a2 = MULSHIFT32(*cptr, b1 - b2) << 2;
    a5 = b5 + b6; a6 = MULSHIFT32(*cptr++, b6 - b5) << 2;

    // Store results back to the buffer
    *--buf = b0; *--buf = b1; *--buf = b2 + b3; *--buf = b3;
    *--buf = b4 + b6; *--buf = b5 + b7; *--buf = b5 + b6; *--buf = b7;
}

By carefully scheduling the arithmetic operations and memory accesses, the number of cycles required to execute the DCT32 function can be reduced, improving overall performance.

4. Fixed-Point Arithmetic Optimization: The MULSHIFT32 macro should be optimized to reduce the number of instructions and cycles required for fixed-point arithmetic. The following code snippet shows an optimized version of the MULSHIFT32 macro:

#define MULSHIFT32(x, y) (((int64_t)(x) * (int64_t)(y)) >> 32)

By combining the multiplication and shift operations into a single instruction, the number of cycles required for fixed-point arithmetic can be reduced, improving performance.

Conclusion

Optimizing C code for the Thumb-1 instruction set on the Cortex-M0+ processor requires careful attention to register allocation, memory access patterns, instruction scheduling, and fixed-point arithmetic. By implementing the optimizations described in this guide, the performance of the DCT32 function in the fixed-point MP3 decoder can be significantly improved, reducing execution time and power consumption. These optimizations are particularly important in resource-constrained embedded systems, where every cycle and every byte of memory counts.