STM32H7 ETM and ETF Configuration Issues Preventing Trace Capture

The STM32H7 microcontroller, based on the ARM Cortex-M7 core, incorporates Embedded Trace Macrocell (ETM) and Embedded Trace FIFO (ETF) modules for real-time instruction trace capture. ETM is responsible for generating trace packets that represent the execution flow of the processor, while ETF acts as a buffer to store these packets before they are read out. In this scenario, the goal is to configure ETM and ETF to capture execution traces in circular buffer mode and subsequently output the trace data via SPI. However, the ETF status register’s READY bit (bit 2 of ETF_STS) never sets, indicating that the trace data is not being captured or stored correctly.

The ETM and ETF modules must be properly initialized and synchronized to ensure trace data flows from ETM to ETF. The ETM generates trace packets based on program flow, and these packets are stored in the ETF’s circular buffer. The ETF’s READY bit indicates that trace data is available for reading. The failure of this bit to set suggests a misconfiguration or synchronization issue between ETM and ETF, or an incorrect setup of the trace capture parameters.

Key components involved in this process include the ETM control registers (ETM_PRGCTRL, ETM_CONFIG, ETM_LAR), ETF control registers (ETF_CTL, ETF_FFCR, ETF_TRG, ETF_LAR), and the Debug Exception and Monitor Control Register (DEMCR). Additionally, the Data Watchpoint and Trace (DWT) unit is used to generate events that trigger ETM trace capture. The DWT comparator (DWT_COMP0) and function register (DWT_FUNCT0) are configured to generate a CMPMATCH event, which is used as a control input to the ETM.

Misconfigured ETM and ETF Registers or Improper Synchronization

One of the primary causes of the ETF READY bit not setting is incorrect configuration of the ETM and ETF registers. The ETM must be unlocked using the ETM_LAR register, and its configuration must be set to enable all relevant trace types. The ETF must also be unlocked and configured to operate in circular buffer mode with appropriate trigger settings. If any of these steps are not performed correctly, trace data will not flow into the ETF, and the READY bit will remain unset.

Another potential cause is improper synchronization between ETM and ETF. The ETM generates trace packets based on program execution, and these packets must be correctly written to the ETF’s buffer. If the ETF is not enabled or configured to accept trace data, the packets will not be stored, and the READY bit will not set. Additionally, the DWT unit must be properly configured to generate the CMPMATCH event, which serves as a trigger for ETM trace capture. If the DWT configuration is incorrect, the ETM will not generate trace packets, and the ETF will remain empty.

The ETF’s Formatter and Flush Control Register (ETF_FFCR) must also be configured correctly. This register controls how trace data is formatted and flushed to the buffer. If the ETF_FFCR is not set according to ARM’s recommendations, trace data may not be written to the buffer correctly, preventing the READY bit from setting. Specifically, the TRIGONTRIGIN, FONTRIGEVT, STOPONFL, ENTI, and ENFT bits must be set as recommended by ARM.

Finally, the ETF’s trigger register (ETF_TRG) must be configured to specify the number of 32-bit words to capture. If this value is set incorrectly, the ETF may not capture the expected amount of trace data, leading to the READY bit remaining unset. The ETF control register (ETF_CTL) must also be enabled to start trace capture. If ETF_CTL is not set, the ETF will not accept trace data from the ETM.

Correcting ETM and ETF Configuration for Successful Trace Capture

To resolve the issue of the ETF READY bit not setting, the following steps should be taken to ensure proper configuration and synchronization of the ETM and ETF modules:

First, verify that the ETM is unlocked and properly configured. The ETM_LAR register must be written with the value 0xC5ACCE55 to unlock the ETM. Once unlocked, the ETM_CONFIG register should be configured to enable all relevant trace types. For example, setting ETM_CONFIG to 0x00031F30 enables all trace types, including instruction trace, data trace, and exception trace. The ETM_PRGCTRL register must then be set to 1 to enable the ETM.

Next, ensure that the ETF is unlocked and configured correctly. The ETF_LAR register must be written with the value 0xC5ACCE55 to unlock the ETF. The ETF_FFCR register should be configured according to ARM’s recommendations, with the TRIGONTRIGIN, FONTRIGEVT, STOPONFL, ENTI, and ENFT bits set. For example, setting ETF_FFCR to 0x00001123 configures the ETF to operate in circular buffer mode with the recommended settings. The ETF_TRG register should be set to specify the number of 32-bit words to capture. For instance, setting ETF_TRG to 16 configures the ETF to capture 16 words of trace data. Finally, the ETF_CTL register must be set to 1 to enable the ETF.

The DWT unit must also be configured to generate the CMPMATCH event, which serves as a trigger for ETM trace capture. The DWT_COMP0 register should be set to the address of the instruction or data to be traced. For example, setting DWT_COMP0 to 0x00000000 configures the DWT to compare against address 0x00000000. The DWT_MASK0 register should be set to specify the number of bits to mask during the comparison. For instance, setting DWT_MASK0 to 24 configures the DWT to compare the upper 8 bits of the address. The DWT_FUNCT0 register should be set to generate the CMPMATCH event. For example, setting DWT_FUNCT0 to 0x00000008 configures the DWT to generate the CMPMATCH[0] event when the comparison matches.

Finally, ensure that the Debug Exception and Monitor Control Register (DEMCR) is configured to enable trace capture. The DEMCR register must have the TRCENA bit (bit 24) set to enable trace functionality. For example, setting DEMCR to (1 << 24) enables trace capture.

Once the ETM, ETF, and DWT are properly configured, the system should be able to capture trace data in circular buffer mode. The ETF’s READY bit (bit 2 of ETF_STS) should set once trace data is available for reading. If the READY bit still does not set, additional debugging may be required to verify the configuration of the ETM, ETF, and DWT registers, as well as the synchronization between these modules.

In summary, the failure of the ETF READY bit to set is likely due to misconfigured ETM and ETF registers or improper synchronization between these modules. By carefully configuring the ETM, ETF, and DWT registers according to ARM’s recommendations, and ensuring proper synchronization, the issue can be resolved, and trace data can be successfully captured in circular buffer mode.

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