ARM ACE Protocol Cache Coherency: SharedClean, SharedDirty, and UniqueDirty State Transitions

Master 1 Writes to SharedClean Cacheline: CleanUnique Transaction and State Transition

In a system utilizing the ARM ACE (AXI Coherency Extensions) protocol, cache coherency is maintained across multiple cache masters connected via a coherent interconnect. Consider a scenario where two cache masters, Master 0 and Master 1, both hold a cacheline in the SharedClean (SC) state. The cacheline size is 64 bytes, and the system is designed to ensure that all caches have a consistent view of memory.

When Master 1 writes to a portion of the shared cacheline, specifically updating the first byte, the ACE protocol dictates specific actions to maintain coherency. Master 1 will issue a CleanUnique transaction to the interconnect. This transaction serves two purposes: it ensures that any other cache holding the line is invalidated, and it transitions the state of the cacheline in Master 1’s cache to UniqueDirty (UD). The UniqueDirty state indicates that Master 1 now holds the only valid copy of the cacheline, and it has been modified.

The interconnect, upon receiving the CleanUnique transaction from Master 1, will issue a CleanInvalid snoop request to Master 0. This snoop request instructs Master 0 to invalidate its copy of the cacheline. Consequently, Master 0’s cacheline transitions from SharedClean to Invalid (I). The final state of the caches after this transaction is:

• Master 1: SharedClean (SC) → UniqueDirty (UD)
• Master 0: SharedClean (SC) → Invalid (I)

This outcome aligns with Result 1 in the original question. The key point here is that the ACE protocol ensures that only one cache master can hold a dirty copy of a cacheline at any given time. This is crucial for maintaining coherency, as it prevents divergent copies of the same cacheline from existing in different caches.

SharedDirty State: When and How It Occurs in ACE Protocol

The SharedDirty (SD) state in the ACE protocol is a less common but important state that can occur under specific conditions. To understand when and how a cacheline transitions to the SharedDirty state, consider a scenario where Master 0 holds a cacheline in the UniqueDirty (UD) state, and Master 1 does not have the cacheline in its cache. If Master 1 issues a ReadShared transaction to the interconnect, the interconnect will snoop Master 0 to obtain the most recent data.

Upon receiving the snoop request, Master 0 will transfer the dirty data to Master 1. After this transfer, the cacheline in Master 0’s cache transitions from UniqueDirty to SharedDirty (SD), indicating that Master 0 still holds a valid copy of the cacheline, but it is now shared with Master 1. Master 1’s cacheline transitions from Invalid to SharedClean (SC). The final state of the caches after this transaction is:

• Master 0: UniqueDirty (UD) → SharedDirty (SD)
• Master 1: Invalid (I) → SharedClean (SC)

Alternatively, Master 0 could pass the dirty data to Master 1 and transition its own cacheline to SharedClean, while Master 1 transitions to SharedDirty. This scenario is less common and depends on the specific implementation of the ACE protocol. The final state in this case would be:

• Master 0: UniqueDirty (UD) → SharedClean (SC)
• Master 1: Invalid (I) → SharedDirty (SD)

It is important to note that not all ACE implementations support the SharedDirty state. Some implementations may use the ReadNotSharedDirty transaction to avoid scenarios where multiple caches hold dirty copies of the same cacheline. This ensures that only one cache master holds a dirty copy at any given time, simplifying coherency management.

Implementing Cache Coherency with ACE: Synchronization and State Management

To effectively implement cache coherency using the ARM ACE protocol, it is essential to understand the various transactions and state transitions that can occur. The following steps outline the key considerations for ensuring proper cache coherency in a system with multiple cache masters:

1. Transaction Issuance and Snooping: When a cache master issues a transaction (e.g., CleanUnique, ReadShared), the interconnect must properly snoop other caches to ensure that the most recent data is obtained and that coherency is maintained. This involves issuing snoop requests to other cache masters and handling the responses appropriately.

2. State Transition Management: Each cache master must correctly transition its cacheline states based on the transactions it issues and the snoop requests it receives. This includes transitioning from SharedClean to UniqueDirty when writing to a cacheline, and from UniqueDirty to SharedDirty or SharedClean when responding to snoop requests.

3. Handling SharedDirty State: If the system supports the SharedDirty state, it is crucial to ensure that this state is managed correctly. This involves understanding when and how the SharedDirty state can occur, and ensuring that the system can handle the associated transactions (e.g., ReadShared, ReadNotSharedDirty) appropriately.

4. Implementation-Specific Considerations: Not all ACE implementations support all possible states and transactions. It is important to understand the specific capabilities and limitations of the ACE implementation being used, and to design the system accordingly. This may involve using transactions like ReadNotSharedDirty to avoid unsupported states.

5. Debugging and Verification: Proper debugging and verification are essential to ensure that cache coherency is maintained in all scenarios. This includes using simulation tools to model the behavior of the cache masters and interconnect, and verifying that the correct state transitions and transactions occur under all conditions.

By following these steps and understanding the intricacies of the ARM ACE protocol, system designers can ensure that cache coherency is maintained across multiple cache masters, preventing data corruption and ensuring reliable system operation.

In conclusion, the ARM ACE protocol provides a robust framework for maintaining cache coherency in systems with multiple cache masters. Understanding the various transactions, state transitions, and implementation-specific considerations is essential for designing and debugging systems that utilize this protocol. By carefully managing cacheline states and ensuring proper synchronization between cache masters, system designers can achieve reliable and efficient operation in complex embedded systems.