ARM Cortex-MAM Mode 1 Performance Anomaly Between LPC2103 and LPC2104
The ARM LPC2103 and LPC2104 microcontrollers, while sharing many architectural similarities, exhibit a significant performance discrepancy when operating in Memory Accelerator Module (MAM) Mode 1. This anomaly manifests as the LPC2103 executing code substantially faster than the LPC2104 under identical conditions, contrary to expectations based on their respective specifications. This issue is particularly puzzling given that both devices are described as having identical MAM Mode 1 behavior, which buffers only sequential code accesses. The observed behavior suggests either a hardware bug, undocumented differences in MAM implementation, or a misinterpretation of the MAM Mode 1 operation between the two devices.
The LPC2103 and LPC2104 are both based on the ARM7TDMI-S core, but they differ in their Flash memory architecture. The LPC2104 features two Flash banks with two buffers for prefetch and branch prediction, while the LPC2103 has a single Flash bank with one buffer. This architectural difference explains the expected performance gap in MAM Mode 2, where the LPC2104’s dual-bank architecture provides a slight advantage. However, the performance inversion in MAM Mode 1, where the LPC2103 outperforms the LPC2104 by a significant margin, cannot be explained by the documented specifications alone.
MAM Mode 1 Implementation Differences and Potential Errata
The root cause of the performance discrepancy in MAM Mode 1 between the LPC2103 and LPC2104 likely lies in one of the following areas: undocumented differences in MAM implementation, a hardware bug in one of the devices, or an errata in the documentation. The MAM is responsible for optimizing Flash memory access by prefetching instructions and buffering sequential code accesses. In MAM Mode 1, only sequential code accesses are buffered, which should theoretically result in similar performance for both devices, given their identical core clock speeds and Flash memory timings.
One possible explanation is that the LPC2103’s MAM implementation in Mode 1 is more aggressive in prefetching sequential instructions, leading to better utilization of the single Flash bank. Conversely, the LPC2104’s dual-bank architecture, while advantageous in MAM Mode 2, may introduce additional latency or inefficiencies in Mode 1 due to the complexity of managing two Flash banks and buffers. This could result in the LPC2104 underperforming relative to the LPC2103 in Mode 1, despite its more advanced memory architecture.
Another possibility is that the LPC2104 has a hardware bug or design flaw that affects its performance in MAM Mode 1. This could involve issues such as incorrect buffer management, suboptimal prefetching logic, or timing errors in the Flash access pipeline. Such a bug would not be immediately apparent in MAM Mode 0 or Mode 2 but could manifest as a significant performance degradation in Mode 1.
Finally, the discrepancy could stem from an errata in the documentation, where the behavior of MAM Mode 1 is inaccurately described for one or both devices. This could lead to incorrect assumptions about the expected performance and behavior of the MAM in Mode 1, resulting in unexpected outcomes when comparing the two devices.
Diagnosing and Resolving MAM Mode 1 Performance Issues
To diagnose and resolve the MAM Mode 1 performance discrepancy between the LPC2103 and LPC2104, the following steps should be taken:
Step 1: Verify MAM Configuration and Timing Settings
Ensure that both devices are configured with identical MAM settings, including clock speeds, Flash memory timings, and MAM mode configurations. Any discrepancies in these settings could lead to performance differences that are unrelated to the MAM implementation itself. Use a logic analyzer or oscilloscope to verify that the timing parameters are being applied correctly and that there are no unexpected delays or glitches in the Flash access pipeline.
Step 2: Analyze Flash Access Patterns
Use a debugger or performance profiling tool to analyze the Flash access patterns of both devices in MAM Mode 1. Compare the number of Flash accesses, the frequency of buffer hits and misses, and the overall efficiency of the prefetching logic. This analysis can reveal whether the LPC2104 is experiencing more frequent buffer misses or longer access latencies compared to the LPC2103, which would explain the performance discrepancy.
Step 3: Investigate MAM Implementation Differences
Review the datasheets and technical reference manuals for both devices to identify any undocumented differences in the MAM implementation. Pay particular attention to the prefetching logic, buffer management, and Flash access pipeline. If possible, consult the manufacturer for additional information or errata related to the MAM behavior in Mode 1.
Step 4: Test with Alternative Code Sequences
Run alternative code sequences on both devices to determine whether the performance discrepancy is consistent across different workloads. Use code sequences with varying degrees of sequential and non-sequential access patterns to assess the impact of MAM Mode 1 on different types of code. This can help identify whether the issue is specific to certain access patterns or is a general performance limitation of the LPC2104 in Mode 1.
Step 5: Implement Workarounds or Optimizations
If the performance discrepancy is confirmed to be a hardware limitation or bug, consider implementing software workarounds or optimizations to mitigate the issue. This could involve adjusting the MAM mode settings, optimizing the code for better sequential access patterns, or using alternative memory access strategies to reduce the impact of the performance discrepancy.
Step 6: Consult Manufacturer for Errata or Firmware Updates
If the issue persists and no satisfactory explanation or workaround is found, consult the manufacturer for any known errata or firmware updates related to the MAM behavior in Mode 1. The manufacturer may have additional insights or solutions that are not publicly documented.
By following these steps, developers can systematically diagnose and address the MAM Mode 1 performance discrepancy between the LPC2103 and LPC2104, ensuring optimal performance and reliability in their embedded systems.
