NIC400 Bus Async FIFO Reset Sequence Issues in Multi-Clock Domain AXI3 Systems

ARESETn and BRESETn Asynchrony Causing Unexpected Data Transfer in NIC400

When designing a system using the ARM NIC400 interconnect with multiple clock domains, one of the critical challenges is managing the reset sequence for asynchronous FIFOs that bridge these domains. In this scenario, the system employs two clock domains: ACLK and BCLK. The NIC400 connects multiple AXI3 slave and master interfaces across these domains, specifically:

• X Slave Interface: Operates on ACLK (AXI3).
• Y Slave Interface: Operates on BCLK (AXI3).
• P Master Interface: Operates on ACLK (AXI3).
• Q Master Interface: Operates on BCLK (AXI3).

The connections are configured as follows:

• X – P: Both operate on ACLK.
• X – Q: X operates on ACLK, Q operates on BCLK.
• Y – P: Y operates on BCLK, P operates on ACLK.
• Y – Q: Both operate on BCLK.

The primary issue arises when asserting the reset signals ARESETn and BRESETn for the Y – P connection. Specifically, when ARESETn is asserted before BRESETn, the asynchronous FIFO’s write pointer in the X – Q connection is reset to 0. This causes the read pointer to increment, leading to the transfer of unexpected values to the Q master interface until BRESETn is asserted. Additionally, the AXI3 interface’s five channels (AW, AR, W, R, B) behave inconsistently during this reset sequence. The valid signals for the AW, AR, and W channels are transferred from Y (BCLK) to P (ACLK), but the read pointer in the asynchronous FIFO is not incremented due to the reset. Conversely, the valid signals for the R and B channels are transferred from P (ACLK) to Y (BCLK), causing the read pointer to increment until BRESETn is asserted.

This behavior highlights a critical flaw in the reset sequence for multi-clock domain systems using the NIC400 interconnect. The asynchronous FIFOs, which are essential for bridging clock domains, are not properly synchronized during reset, leading to data corruption and unexpected transfers. This issue is particularly problematic in systems where precise timing and data integrity are paramount, such as in high-performance computing or real-time embedded systems.

Misaligned Reset Assertion and FIFO Pointer Synchronization

The root cause of this issue lies in the misaligned assertion of ARESETn and BRESETn and the lack of proper synchronization mechanisms for the asynchronous FIFOs during reset. When ARESETn is asserted, it immediately resets the write pointer of the asynchronous FIFO in the X – Q connection to 0. However, the read pointer, which operates in the BCLK domain, continues to increment because BRESETn has not yet been asserted. This misalignment between the write and read pointers leads to the transfer of invalid data.

Furthermore, the AXI3 protocol’s reliance on five independent channels exacerbates the problem. The AW, AR, and W channels, which transfer data from Y (BCLK) to P (ACLK), do not increment the read pointer in the asynchronous FIFO because the reset signal ARESETn is already active. However, the R and B channels, which transfer data from P (ACLK) to Y (BCLK), continue to increment the read pointer until BRESETn is asserted. This inconsistency in channel behavior during reset creates a race condition, leading to data corruption.

Another contributing factor is the lack of a unified reset strategy for multi-clock domain systems. The NIC400 interconnect does not inherently provide a mechanism to synchronize reset signals across clock domains, leaving it up to the designer to implement a robust reset sequence. Without a well-defined reset sequence, the asynchronous FIFOs are vulnerable to pointer misalignment, which can result in data loss or corruption.

Implementing a Synchronized Reset Sequence and FIFO Management Strategy

To address this issue, a comprehensive reset sequence and FIFO management strategy must be implemented. The following steps outline a solution to ensure proper synchronization of reset signals and FIFO pointers across multiple clock domains:

1. Synchronized Reset Assertion and De-assertion:

   • Implement a reset synchronization circuit that ensures ARESETn and BRESETn are asserted and de-asserted in a coordinated manner. This can be achieved using a series of flip-flops to synchronize the reset signals across clock domains.
   • Ensure that ARESETn and BRESETn are de-asserted simultaneously to prevent any misalignment in the asynchronous FIFO pointers.

2. FIFO Pointer Initialization:

   • Modify the asynchronous FIFO design to include a reset mechanism that initializes both the write and read pointers simultaneously when either ARESETn or BRESETn is asserted. This ensures that the FIFO is in a known state before any data transfer begins.
   • Implement a handshake mechanism between the write and read pointers to ensure that they are properly synchronized during reset.

3. AXI Channel Management:

   • Introduce a state machine to manage the AXI channels during reset. This state machine should ensure that all channels are properly initialized and that no data is transferred until both ARESETn and BRESETn are de-asserted.
   • Use the AXI protocol’s built-in handshake signals (e.g., AWVALID, WVALID, ARVALID, RVALID, BVALID) to ensure that no invalid data is transferred during the reset sequence.

4. Clock Gating and Isolation:

   • Implement clock gating to disable the clocks for the asynchronous FIFOs during reset. This prevents any increment of the read or write pointers until the reset sequence is complete.
   • Use isolation cells to ensure that no spurious signals are propagated through the FIFOs during reset.

5. Verification and Testing:

   • Develop a comprehensive verification plan to test the reset sequence and FIFO management strategy. This should include corner cases such as partial resets, power-on resets, and reset glitches.
   • Use simulation tools to model the behavior of the asynchronous FIFOs and AXI channels during reset. This will help identify any potential issues before the design is implemented in hardware.

By implementing these steps, the issues related to the reset sequence in multi-clock domain systems using the NIC400 interconnect can be effectively mitigated. This approach ensures that the asynchronous FIFOs are properly synchronized, and the AXI channels are managed correctly during reset, leading to a more robust and reliable system design.

Detailed Analysis of Reset Synchronization and FIFO Management

To further elaborate on the proposed solution, let’s delve into the technical details of each step:

Synchronized Reset Assertion and De-assertion

The reset synchronization circuit is crucial for ensuring that ARESETn and BRESETn are properly aligned. This circuit typically consists of a series of flip-flops that are used to synchronize the reset signals across clock domains. The following table outlines the steps involved in this process:

Step	Description
1	Assert ARESETn in the ACLK domain.
2	Synchronize ARESETn to the BCLK domain using a series of flip-flops.
3	Assert BRESETn in the BCLK domain.
4	Synchronize BRESETn to the ACLK domain using a series of flip-flops.
5	De-assert ARESETn and BRESETn simultaneously in both clock domains.

This synchronization ensures that both reset signals are aligned, preventing any misalignment in the asynchronous FIFO pointers.

FIFO Pointer Initialization

The asynchronous FIFO design must be modified to include a reset mechanism that initializes both the write and read pointers simultaneously. This can be achieved by adding a reset signal to the FIFO control logic that is triggered by either ARESETn or BRESETn. The following steps outline the process:

1. Reset Signal Generation: Generate a combined reset signal that is asserted when either ARESETn or BRESETn is asserted.
2. Pointer Initialization: Use the combined reset signal to initialize both the write and read pointers to 0.
3. Handshake Mechanism: Implement a handshake mechanism between the write and read pointers to ensure that they are properly synchronized during reset.

AXI Channel Management

The state machine for managing the AXI channels during reset should be designed to ensure that all channels are properly initialized and that no data is transferred until both ARESETn and BRESETn are de-asserted. The following steps outline the process:

1. State Machine Design: Design a state machine that transitions through different states based on the status of ARESETn and BRESETn.
2. Channel Initialization: In the reset state, initialize all AXI channels to their default values.
3. Handshake Signal Management: Use the AXI protocol’s built-in handshake signals to ensure that no invalid data is transferred during the reset sequence.

Clock Gating and Isolation

Clock gating and isolation are essential for preventing any increment of the read or write pointers during reset. The following steps outline the process:

1. Clock Gating: Implement clock gating to disable the clocks for the asynchronous FIFOs during reset.
2. Isolation Cells: Use isolation cells to ensure that no spurious signals are propagated through the FIFOs during reset.

Verification and Testing

A comprehensive verification plan is essential for ensuring that the reset sequence and FIFO management strategy are effective. The following steps outline the process:

1. Verification Plan Development: Develop a verification plan that includes corner cases such as partial resets, power-on resets, and reset glitches.
2. Simulation: Use simulation tools to model the behavior of the asynchronous FIFOs and AXI channels during reset.
3. Testing: Perform extensive testing to identify any potential issues before the design is implemented in hardware.

By following these detailed steps, the issues related to the reset sequence in multi-clock domain systems using the NIC400 interconnect can be effectively mitigated. This approach ensures that the asynchronous FIFOs are properly synchronized, and the AXI channels are managed correctly during reset, leading to a more robust and reliable system design.