ARM Cortex-R5 Heroncell_DCCM Module fault_s Signal Unknown at Power-Up
The fault_s signal in the Heroncell_DCCM module of the ARM Cortex-R5 is holding an unknown value (X) during the power-up sequence. This issue arises during the SOC_FSM_WAIT_POR_STABLE state, where the fault_s signal is asserted with the clock running. The unknown value propagates to the dccmout and dccmout2 signals of the Cortex-R5, leading to a "Fault Signal Level Error" in the SAFETY function. This error occurs before the system transitions out of the SOC_FSM_WAIT_POR_STABLE state, which is critical for ensuring proper initialization of the SoC.
The Heroncell_DCCM module is responsible for managing the Data Closely Coupled Memory (DCCM) in the Cortex-R5. The fault_s signal is a critical signal that indicates whether a fault condition has been detected in the DCCM. During power-up, the signal should be in a known state (either high or low) to ensure proper initialization of the DCCM and avoid erroneous fault detection. The unknown value on fault_s can lead to incorrect behavior in the DCCM, potentially causing data corruption or system instability.
The issue is further complicated by the presence of a dual-CPU system, where the Cortex-R5 wakes up before the Cortex-A65. The unknown value on fault_s in the Cortex-R5 could potentially affect the initialization sequence of the Cortex-A65, leading to cross-CPU synchronization issues. This is particularly problematic in safety-critical applications where the SAFETY function is used to monitor and ensure the correct operation of the system.
Power-On Reset (POR) Timing and Signal Initialization Issues
The root cause of the unknown value on the fault_s signal during power-up can be attributed to several factors related to the Power-On Reset (POR) timing and signal initialization sequence. The SOC_FSM_WAIT_POR_STABLE state is designed to wait for the POR signal to stabilize before proceeding with the initialization of the system. However, if the fault_s signal is not properly initialized during this state, it can lead to the propagation of unknown values.
One possible cause is the improper sequencing of the reset signals. The reset signal for the Heroncell_DCCM module may not be asserted long enough to ensure that all internal registers and signals, including fault_s, are properly initialized. This can result in the fault_s signal being left in an unknown state when the clock starts running. Additionally, the reset signal may not be synchronized with the clock, leading to metastability issues that can cause the fault_s signal to hold an unknown value.
Another potential cause is the lack of proper initialization values for the fault_s signal in the RTL design. If the fault_s signal is not explicitly initialized to a known value (either high or low) in the RTL code, it can default to an unknown state during simulation. This is particularly problematic in gate-level simulations where the initial state of signals can have a significant impact on the behavior of the design.
The interaction between the Cortex-R5 and Cortex-A65 during the power-up sequence can also contribute to the issue. If the Cortex-R5 is not fully initialized before the Cortex-A65 starts its initialization sequence, it can lead to cross-CPU synchronization issues. This can result in the fault_s signal being left in an unknown state, as the Cortex-R5 may not have completed its initialization before the Cortex-A65 starts accessing shared resources.
Implementing Proper Reset Sequencing and Signal Initialization
To resolve the issue of the unknown value on the fault_s signal during power-up, it is essential to implement proper reset sequencing and signal initialization in the Heroncell_DCCM module. The following steps outline the necessary actions to ensure that the fault_s signal is properly initialized and does not propagate unknown values during the power-up sequence.
First, ensure that the reset signal for the Heroncell_DCCM module is asserted for a sufficient duration to allow all internal registers and signals to be properly initialized. The reset signal should be synchronized with the clock to avoid metastability issues. This can be achieved by using a synchronizer circuit that ensures the reset signal is stable before it is used to initialize the module.
Next, explicitly initialize the fault_s signal to a known value in the RTL code. This can be done by setting the initial value of the fault_s signal to either high or low in the RTL design. This ensures that the fault_s signal starts in a known state during simulation and does not default to an unknown value. Additionally, ensure that the initialization value is consistent with the expected behavior of the fault_s signal during normal operation.
To address cross-CPU synchronization issues, implement a handshake mechanism between the Cortex-R5 and Cortex-A65 during the power-up sequence. This ensures that the Cortex-R5 is fully initialized before the Cortex-A65 starts its initialization sequence. The handshake mechanism can be implemented using a shared register or a dedicated signal that indicates when the Cortex-R5 has completed its initialization. This prevents the Cortex-A65 from accessing shared resources before the Cortex-R5 is ready, reducing the risk of synchronization issues.
Finally, perform thorough verification of the reset sequencing and signal initialization using both RTL and gate-level simulations. This includes verifying that the fault_s signal is properly initialized and does not propagate unknown values during the power-up sequence. Use assertion-based verification to monitor the behavior of the fault_s signal and ensure that it remains in a known state throughout the power-up sequence. Additionally, perform timing analysis to ensure that the reset signal is asserted for a sufficient duration and is properly synchronized with the clock.
By implementing these steps, the issue of the unknown value on the fault_s signal during power-up can be resolved, ensuring proper initialization of the Heroncell_DCCM module and avoiding erroneous fault detection in the SAFETY function. This will improve the reliability and stability of the ARM-based SoC, particularly in safety-critical applications where proper initialization is critical for ensuring correct operation.
