AHB5 Write Strobes: Active vs. Inactive Byte Lane Behavior

AHB5 Write Strobes and Byte Lane Activation Rules

The AHB5 protocol introduces the concept of write strobes (HWSTRB) to provide finer control over data transfers, particularly for sparse writes. The behavior of HWSTRB signals is governed by the HADDR (address) and HSIZE (transfer size) signals, which determine the active and inactive byte lanes for a given transfer. According to the ARM IHI 0033C specification, the rules for write strobes are defined in Section 3.5.2. These rules state that:

1. Active Byte Lanes: Write strobes corresponding to active byte lanes can be either HIGH or LOW. A transfer with LOW strobe bits for active byte lanes is referred to as a sparse write.
2. Inactive Byte Lanes: Write strobes corresponding to inactive byte lanes can also be HIGH or LOW. The interface must use HSIZE and HADDR to determine which byte lanes are inactive.

At first glance, these rules may appear contradictory because they allow HWSTRB bits to be either HIGH or LOW for both active and inactive byte lanes. However, the key distinction lies in how the manager and subordinate interpret these signals. The manager uses HADDR and HSIZE to define the active byte lanes, and the subordinate uses the same signals to determine which byte lanes are relevant for the transfer. The HWSTRB signals are only meaningful for active byte lanes, as they indicate whether the corresponding byte lane contains valid data. For inactive byte lanes, the HWSTRB values are irrelevant because those lanes cannot be used for the transfer.

This behavior is critical for ensuring backward compatibility with earlier versions of the AHB protocol, where write strobes were not supported. In such cases, the manager would drive all HWSTRB signals HIGH by default, effectively treating all byte lanes as active. With the introduction of HWSTRB in AHB5, the protocol allows for more efficient data transfers by enabling sparse writes, where only specific byte lanes within the active range are updated.

Conflicting Interpretations of HWSTRB Signal Descriptions

The confusion in the discussion arises from the interpretation of the HWSTRB signal descriptions in different sections of the ARM IHI 0033C specification. Specifically, Section 2.2 (Manager Signals) states that the HWSTRB signal is "deasserted to indicate when active write data byte lanes do not contain valid data." This description implies that the HWSTRB signal is only relevant for active byte lanes, as defined by HADDR and HSIZE. However, Section 3.5.2 (Write Strobes Rules) allows HWSTRB bits to be either HIGH or LOW for both active and inactive byte lanes.

This apparent contradiction can be resolved by understanding the context in which these descriptions are provided. Section 2.2 focuses on the behavior of the HWSTRB signal from the manager’s perspective, emphasizing its role in indicating valid data for active byte lanes. In contrast, Section 3.5.2 provides a more comprehensive view of the HWSTRB signal’s behavior, including its treatment of inactive byte lanes. The key takeaway is that the HWSTRB signal is only meaningful for active byte lanes, as determined by HADDR and HSIZE. For inactive byte lanes, the HWSTRB values are irrelevant and do not affect the transfer.

To further clarify, consider the following scenarios:

1. Manager Does Not Support Write Strobes: In this case, the manager drives all HWSTRB signals HIGH by default, effectively treating all byte lanes as active. This behavior ensures backward compatibility with earlier versions of the AHB protocol.
2. Manager Supports Write Strobes: The manager uses HADDR and HSIZE to define the active byte lanes and drives the corresponding HWSTRB signals HIGH or LOW to indicate valid data. For inactive byte lanes, the HWSTRB values are irrelevant and can be either HIGH or LOW.

The subordinate, on the other hand, uses HADDR and HSIZE to determine the active byte lanes and interprets the HWSTRB signals accordingly. For inactive byte lanes, the subordinate ignores the HWSTRB values, as those lanes are not part of the transfer.

Resolving HWSTRB Behavior for Managers and Subordinates Supporting Write Strobes

When both the manager and subordinate support the write strobes property, the behavior of the HWSTRB signals becomes more nuanced. The manager must ensure that the HWSTRB signals are driven correctly to indicate valid data for active byte lanes, while the subordinate must interpret these signals accurately to perform the transfer.

The following steps outline the process for resolving HWSTRB behavior in this scenario:

1. Determine Active Byte Lanes: The manager uses HADDR and HSIZE to determine the active byte lanes for the transfer. For example, if HSIZE indicates a 32-bit transfer and HADDR is aligned to a 4-byte boundary, the active byte lanes are lanes 0 through 3.
2. Drive HWSTRB Signals: The manager drives the HWSTRB signals corresponding to the active byte lanes HIGH or LOW to indicate valid data. For example, if the manager wants to perform a sparse write, it may drive HWSTRB[0] and HWSTRB[2] HIGH while driving HWSTRB[1] and HWSTRB[3] LOW.
3. Ignore Inactive Byte Lanes: The manager can drive the HWSTRB signals corresponding to inactive byte lanes HIGH or LOW, as these values are irrelevant. The subordinate will ignore these signals because the corresponding byte lanes are not part of the transfer.
4. Subordinate Interpretation: The subordinate uses HADDR and HSIZE to determine the active byte lanes and interprets the HWSTRB signals accordingly. For example, if HSIZE indicates a 32-bit transfer and HADDR is aligned to a 4-byte boundary, the subordinate will only consider HWSTRB[0:3] for the transfer.

To illustrate this process, consider the following example:

• HADDR: 0x1000 (aligned to a 4-byte boundary)
• HSIZE: 32-bit transfer
• HWSTRB: 4’b1010 (HWSTRB[0] and HWSTRB[2] are HIGH; HWSTRB[1] and HWSTRB[3] are LOW)

In this case, the manager is performing a sparse write, updating only byte lanes 0 and 2. The subordinate will interpret the HWSTRB signals and update only the specified byte lanes, leaving byte lanes 1 and 3 unchanged.

Table: HWSTRB Signal Behavior for Active and Inactive Byte Lanes

Byte Lane	Active/Inactive	HWSTRB Value	Interpretation by Subordinate
0	Active	HIGH	Valid data; update byte lane 0
1	Active	LOW	Invalid data; do not update byte lane 1
2	Active	HIGH	Valid data; update byte lane 2
3	Active	LOW	Invalid data; do not update byte lane 3
4	Inactive	HIGH/LOW	Irrelevant; ignore byte lane 4
5	Inactive	HIGH/LOW	Irrelevant; ignore byte lane 5
6	Inactive	HIGH/LOW	Irrelevant; ignore byte lane 6
7	Inactive	HIGH/LOW	Irrelevant; ignore byte lane 7

This table summarizes the behavior of the HWSTRB signals for both active and inactive byte lanes. The subordinate only considers the HWSTRB signals for active byte lanes, as determined by HADDR and HSIZE. For inactive byte lanes, the HWSTRB values are irrelevant and do not affect the transfer.

Practical Considerations for HWSTRB Implementation

When implementing HWSTRB signals in an AHB5-compliant design, the following considerations should be taken into account:

1. Backward Compatibility: Ensure that the manager drives all HWSTRB signals HIGH by default if write strobes are not supported. This ensures compatibility with earlier versions of the AHB protocol.
2. Sparse Writes: Use HWSTRB signals to enable sparse writes, where only specific byte lanes within the active range are updated. This can improve efficiency by reducing unnecessary data transfers.
3. Subordinate Behavior: Ensure that the subordinate correctly interprets the HWSTRB signals based on HADDR and HSIZE. The subordinate should only update byte lanes corresponding to active HWSTRB signals.
4. Verification: Thoroughly verify the behavior of the HWSTRB signals using simulation and formal verification techniques. This includes testing edge cases, such as sparse writes and transfers with varying HSIZE values.

By following these guidelines, designers can ensure that their AHB5-compliant designs correctly implement the HWSTRB signals and achieve the desired behavior for both active and inactive byte lanes.

Conclusion

The behavior of HWSTRB signals in the AHB5 protocol is governed by the HADDR and HSIZE signals, which determine the active and inactive byte lanes for a given transfer. While the specification allows HWSTRB bits to be either HIGH or LOW for both active and inactive byte lanes, the key distinction lies in how these signals are interpreted by the manager and subordinate. The HWSTRB signals are only meaningful for active byte lanes, as they indicate whether the corresponding byte lane contains valid data. For inactive byte lanes, the HWSTRB values are irrelevant and do not affect the transfer.

By understanding the rules and context provided in the ARM IHI 0033C specification, designers can resolve any apparent contradictions and correctly implement HWSTRB signals in their AHB5-compliant designs. This ensures efficient data transfers, backward compatibility, and accurate interpretation of write strobes by both managers and subordinates.