Cortex-R52 SPI Interrupt Routing to PEs Failure Analysis

Cortex-R52 SPI Interrupt Routing to PEs Not Functioning

GIC Configuration and Affinity Routing Issues

The core issue revolves around the inability to route Shared Peripheral Interrupts (SPIs) to Processing Elements (PEs) other than core 0 in a Cortex-R52 multicore setup. The Generic Interrupt Controller (GIC) is configured to use affinity routing, as indicated by the ARE_S bit being set in the GICD_CTLR register. This setup implies that interrupts should be distributable across multiple cores based on the GICD_IROUTER register settings. However, while interrupts are successfully routed to core 0, they fail to reach core 1 despite the pending flag being set in the GIC Distributor.

The GICD_IROUTER registers are responsible for defining the target PE for each interrupt. When an interrupt is triggered by writing to the GICD_ISPENDR register, the pending flag is set in the GIC Distributor, but the GIC CPU interface of core 1 does not reflect this pending interrupt. This discrepancy suggests a breakdown in the interrupt routing mechanism between the GIC Distributor and the CPU interface of core 1.

The Cortex-R52’s GIC implementation requires careful configuration of both the Distributor and CPU interfaces. The ARE_S bit in the GICD_CTLR register enables affinity routing for secure state, which is necessary for multicore interrupt distribution. However, enabling this bit alone is insufficient if other critical configurations are overlooked. For instance, the GICC_PMR (Priority Mask Register) of core 1 is set to allow all priorities, which rules out priority masking as the cause of the issue.

Potential Misconfigurations in GIC and CPU Interfaces

Several potential causes could explain why SPI interrupts are not being routed to core 1. First, the CPU interface on core 1 might not be fully initialized or enabled. While the user confirmed that the CPU interface is enabled and that timer interrupts (PPI source 30) are functioning on core 1, this does not guarantee that the SPI routing logic is correctly configured. The GIC initialization code must be executed on each core to ensure that the CPU interface is properly set up. If this step is missed, the CPU interface might not be ready to accept SPIs.

Second, the GICD_IROUTER register settings might be incorrect or misaligned. The user mentioned that the same code works for core 0 without setting the IROUTER register, which implies that the default routing for core 0 is functioning as expected. However, when attempting to route interrupts to core 1, the target register might not be correctly configured. The GICD_IROUTER registers are 64-bit registers, and their lower 32 bits define the target PE. If the target PE value is incorrect or misaligned, the interrupt will not be routed to the intended core.

Third, there could be an issue with the interrupt vector table or the interrupt handler configuration on core 1. While the pending flag is set in the GIC Distributor, the CPU interface might not be acknowledging the interrupt due to a misconfigured vector table or handler. This could result in the interrupt being ignored or mishandled.

Fourth, the GIC Distributor’s ARE_S bit might not be fully compatible with the Cortex-R52’s implementation. While the ARE_S bit enables affinity routing, there could be additional requirements or constraints specific to the Cortex-R52 that are not documented or well-understood. This could include specific timing requirements for setting the GICD_IROUTER registers or additional configuration steps in the GIC Distributor.

Comprehensive Debugging and Configuration Steps

To resolve the SPI interrupt routing issue, a systematic approach is required to verify and correct the GIC and CPU interface configurations. The following steps outline a detailed troubleshooting process:

1. Verify CPU Interface Initialization on Core 1: Ensure that the GIC initialization code is executed on core 1. This includes setting up the GICC_CTLR (CPU Interface Control Register) and GICC_PMR (Priority Mask Register). Confirm that the CPU interface is enabled and ready to accept interrupts. Use a debugger to inspect the GICC_CTLR and GICC_PMR registers on core 1 to verify their values.

2. Check GICD_IROUTER Register Settings: Double-check the GICD_IROUTER register settings for the SPI being tested. Ensure that the lower 32 bits of the register correctly specify the target PE (core 1). Use a debugger to inspect the GICD_IROUTER register and confirm that the target PE value is correct. If necessary, manually set the register using a debugger to rule out any software configuration issues.

3. Inspect Interrupt Vector Table and Handler: Verify that the interrupt vector table and handler are correctly configured on core 1. Ensure that the vector table base address is correctly set and that the handler for the SPI is properly defined. Use a debugger to inspect the vector table and confirm that the handler address is correct.

4. Test with Different Interrupt Sources: Test the interrupt routing with different SPI sources to rule out any issues specific to the current interrupt being tested. If possible, use a hardware-based interrupt source (e.g., a peripheral) instead of manually triggering the interrupt using the GICD_ISPENDR register.

5. Review Cortex-R52 GIC Implementation: Consult the Cortex-R52 Technical Reference Manual (TRM) and the GIC Architecture Specification to identify any additional configuration steps or constraints specific to the Cortex-R52. Pay particular attention to the timing requirements for setting the GICD_IROUTER registers and any additional configuration steps in the GIC Distributor.

6. Enable Debugging Features: Use the Cortex-R52’s debugging features to trace the interrupt routing process. Enable the GIC’s debugging features (if available) to monitor the interrupt routing in real-time. Use a logic analyzer or oscilloscope to monitor the interrupt signals and confirm that they are being correctly routed to core 1.

7. Check for Hardware Issues: If all software configurations appear correct, consider the possibility of a hardware issue. Inspect the board design and schematics to ensure that the interrupt signals are correctly connected to core 1. Use a multimeter or oscilloscope to verify the signal integrity of the interrupt lines.

By following these steps, the root cause of the SPI interrupt routing issue can be identified and resolved. The key is to systematically verify each component of the GIC and CPU interface configuration, ensuring that all settings are correct and compatible with the Cortex-R52’s implementation.