ARM Cortex-ETM Trace Configuration and ATVALID Signal Failure
The ARM Embedded Trace Macrocell (ETM) is a critical component for real-time instruction tracing in ARM-based systems, enabling developers to capture and analyze the execution flow of their software. The ATVALID signal, which indicates that the trace unit is ready to output valid trace data, is a key indicator of proper ETM functionality. When ATVALID fails to assert, it suggests that the trace unit is either misconfigured or encountering a hardware-software interaction issue. This issue is particularly relevant when working with ARM Cortex processors that implement the Embedded Trace Extension (ETE), as the configuration sequence and register settings must align precisely with the architecture specifications.
The problem described involves a scenario where the ATVALID signal does not assert after following the ETM configuration sequence outlined in the ARM IHI0064H.b document. The user has verified several status registers, including TRCLSR, TRCOSLSR, TRCPDSR, TRCSTATR, EDSCR, and EDPRSR, to ensure that the software and OS locks are cleared, the trace unit is powered, and the trace feature is enabled. Despite these checks, the ATVALID signal remains inactive, preventing the capture of instruction trace data.
This issue is often rooted in subtle misconfigurations or timing issues within the ETM and its associated debug registers. The ETM relies on a precise sequence of register writes and reads to initialize its state, and any deviation from this sequence can result in the trace unit failing to enter the correct operational mode. Additionally, the interaction between the ETM and the CPU core, particularly in multi-core systems, can introduce complexities that are not immediately apparent from the documentation alone.
Potential Misconfigurations in ETM Registers and Debug Logic
One of the primary causes of ATVALID not asserting is an incomplete or incorrect configuration of the ETM registers. The ARM IHI0064H.b document provides a detailed sequence for configuring the ETM, but it assumes a specific hardware and software environment. Deviations from this environment, such as differences in the SoC implementation or the use of custom firmware, can lead to unexpected behavior.
The TRCLSR register, which controls the software lock status, must be correctly configured to ensure that the ETM is not locked. The user has confirmed that TRCLSR.SLK is cleared, indicating that the software lock is not active. However, other fields in TRCLSR, such as TRCLSR.SLI, must also be checked to ensure that the software lock mechanism is implemented and functioning as expected. Similarly, the TRCOSLSR register, which controls the OS lock status, must be configured to clear the OS lock and enable access to the trace registers.
The TRCPDSR register provides additional status information, including the power state of the trace unit and the validity of the trace registers. The user has verified that TRCPDSR.POWER is set, indicating that the trace unit is powered, and TRCPDSR.STICKYPD is cleared, indicating that the trace registers are valid. However, other fields in TRCPDSR, such as TRCPDSR.OSLK, must also be checked to ensure that the OS lock is cleared and the trace unit is ready to operate.
The EDSCR register, which controls the debug status and control, must be configured to enable the trace feature and ensure that instruction execution is advancing. The user has confirmed that EDSCR.TFO is set, indicating that the trace feature is enabled, and EDSCR.PIPEADV is set, indicating that instruction execution is occurring. However, other fields in EDSCR, such as EDSCR.HDE, must also be checked to ensure that the debug logic is properly configured.
The EDPRSR register, which controls the debug power and reset status, must be configured to ensure that the trace unit is not held in a reset state. The user has confirmed that EDPRSR.OSLK is cleared, indicating that the OS lock is not active. However, other fields in EDPRSR, such as EDPRSR.PRST, must also be checked to ensure that the trace unit is not held in a reset state.
Comprehensive Debugging and Configuration Steps for ATVALID Assertion
To resolve the issue of ATVALID not asserting, a comprehensive debugging and configuration approach is required. This approach involves verifying the configuration of all relevant ETM and debug registers, ensuring that the trace unit is properly initialized, and checking for any hardware or software issues that may be preventing the trace unit from operating correctly.
The first step is to verify the configuration of the TRCLSR register. This register controls the software lock status and must be configured to ensure that the ETM is not locked. The TRCLSR.SLK field must be cleared to indicate that the software lock is not active, and the TRCLSR.SLI field must be set to indicate that the software lock mechanism is implemented. If either of these fields is not set correctly, the ETM will not be able to operate.
The next step is to verify the configuration of the TRCOSLSR register. This register controls the OS lock status and must be configured to ensure that the OS lock is cleared and the trace registers are accessible. The TRCOSLSR.OSLM field must be set to indicate that the OS lock is implemented, and the TRCOSLSR.OSLK field must be cleared to indicate that the OS lock is not active. If either of these fields is not set correctly, the ETM will not be able to operate.
The TRCPDSR register must also be verified to ensure that the trace unit is powered and the trace registers are valid. The TRCPDSR.POWER field must be set to indicate that the trace unit is powered, and the TRCPDSR.STICKYPD field must be cleared to indicate that the trace registers are valid. If either of these fields is not set correctly, the ETM will not be able to operate.
The EDSCR register must be configured to enable the trace feature and ensure that instruction execution is advancing. The EDSCR.TFO field must be set to indicate that the trace feature is enabled, and the EDSCR.PIPEADV field must be set to indicate that instruction execution is occurring. Additionally, the EDSCR.HDE field must be checked to ensure that the debug logic is properly configured. If any of these fields is not set correctly, the ETM will not be able to operate.
The EDPRSR register must be configured to ensure that the trace unit is not held in a reset state. The EDPRSR.OSLK field must be cleared to indicate that the OS lock is not active, and the EDPRSR.PRST field must be checked to ensure that the trace unit is not held in a reset state. If either of these fields is not set correctly, the ETM will not be able to operate.
In addition to verifying the configuration of the ETM and debug registers, it is also important to check for any hardware or software issues that may be preventing the trace unit from operating correctly. This includes checking for any timing issues in the configuration sequence, ensuring that the trace unit is properly connected to the CPU core, and verifying that the firmware is correctly initializing the trace unit.
If the above steps do not resolve the issue, it may be necessary to perform a more detailed analysis of the trace unit and its interaction with the CPU core. This may involve using a logic analyzer to capture the signals between the trace unit and the CPU core, or using a debugger to step through the firmware and verify the configuration sequence.
In conclusion, the issue of ATVALID not asserting is often caused by subtle misconfigurations or timing issues within the ETM and its associated debug registers. By following a comprehensive debugging and configuration approach, it is possible to identify and resolve these issues, enabling the trace unit to operate correctly and capture the desired instruction trace data.
